FABulous: An Embedded FPGA Framework

Koch, Dirk; Dao, Nguyen Cong; Healy, Bea; Yu, Jing; Attwood, Andrew

doi:10.1145/3431920.3439302

Cited by 34 publications

(24 citation statements)

References 23 publications

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“…This research has a long history. For example, custom cells were deployed in [1], [13]- [15] to improved design metrics, or the work in [16] discussed the effect of floorplanning on FPGA performance (latency). [17] discusses if pass-gates or transmission gates are better suited for building custom multiplexers for FPGAs, and customizing and optimizing the architecture of FPGAs are studied deeply in [18], [19].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Even these configuration bit output wires are not timing critical, they will still create a force during place and route of the tile when the primitives and routing fabric have to be implemented together with the configuration bit cells. Therefore, the mapping of configuration bits into frames and frame positions (for frame-based configuration -FBC) or the order inside a configuration shift-register (for shift-register 1 The Skywater standard cell library provides a Mux4 primitive that is 9.66 × 2.72µm 2 , but the Yosys tool was falling back to use a Mux2 and some logic instead (using an accumulated size of 12.42 × 2.72µm 2 ). We found a similar behavior when studying the OpenFPGA GDS in [25].…”

Section: Configuration Cell Placementmentioning

confidence: 99%

“…FD [1] FD [2] FD [3] FD [4] FD [5] FS [1] FS [2] FS [3] FS [4] FS [ use the Google Optimization tool (OR tools [28]) to solve the assignment problem on that matrix. The used mixed integer programming solver minimizes the distance between each of the memory cells and the grid locations while assigning each of the memory cells a coordinate.…”

Section: A Algorithm and Implementationmentioning

confidence: 99%

“…To illustrate the complexity of designing FPGAs (or embedded FPGAs -eFPGAs), Figure 1 shows the FABulous ecosystem [1] that itself integrates several industry and opensource tools to generate the physical FPGA ASIC implementation as well as a flow to compile user circuits into bitstreams. Fabulous provides flows for physically implementing an FPGA fabric on a chip and for parametrizing the SymbiFlow [2] open-source tool suite that is integrating Yosys [3], nextpnr [4], ABC [5] and VPR [6] that is used to compile Verilog to bitstreams for the FPGA fabics.…”

Section: Introductionmentioning

confidence: 99%

“…1. FABulous [1] integrates academic and industry tools for ASIC generation, emulation (not shown), and eFPGA configuration bitstream generation.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics

Chung

Dao

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Commercial FPGAs from major vendors are extensively optimized, and fabrics use many hand-crafted custom cells, including switch matrix multiplexers and configuration memory cells. The physical design optimizations commonly improve area, latency (=speed), and power consumption together. This paper is dedicated to improving the physical implementation of FPGA tiles and the configuration storage in SRAM FPGAs. This paper proposes to remap configuration bits and interface wires to implement tightly packed tiles. Using the FABulous FPGA framework, we show that our optimizations are virtually for free but can save over 20% in area and improve latency at the same time. We will evaluate our approach in different scenarios by changing the available metal layers or the requested channel capacity. Our optimizations consider all tiles and we propose a flow that resolves dependencies between CLB and other tiles. Moreover, we will show that frame-based reconfiguration is, in almost all cases, better than shift register configuration.

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