Facile Transferring of Wafer-Scale Ultrathin Alumina Membranes onto Substrates for Nanostructure Patterning

Abstract

Ordered nanostructure arrays have attracted intensive attention because of their various applications. However, it is still a great challenge to achieve ordered nanostructure patterning over a large area (such as wafer-scale) by a technique that allows high throughput, large pattern area and low equipment costs. Here, through a unique design of the fabrication and transferring processes, we achieve a facile transferring of wafer-scale ultrathin alumina membranes (UTAMs) onto substrates without any twisting, folding, cracking and contamination. The most important in our method is fixing the UTAM onto the wafer-scale substrate before removing the backside Al and alumina barrier layer. It is also demonstrated that the thickness and surface smoothing of UTAMs play crucial roles in this transferring process. By using these perfectly transferred UTAMs as masks, various nanostructure patterning including nanoparticle, nanopore (nanomesh) and nanowire arrays are fabricated on wafer-scale substrates with tunable and uniform dimension. Because there are no requirements for UTAMs, substrates and materials to be deposited, the method presented here shall provide a cost-effective platform for the fabrication of ordered nanostructures on large substrates for various applications in nanotechnology.

Controlled and Selective Growth of 1D and 3D CdTe Nanostructures through a Structurally Engineered Porous Alumina Template for Enhanced Optical Applications

“…Previous literatures by Haddad et al and Meng et al demonstrated large area fabrication and transfer of PA membrane onto perfect flat Silicon (Si) substrate. 33,38 However, authors used sophisticated ion milling technique to remove and flatten the barrier layer for transfer onto Si substrate, which needs a high precision as well as a high expense. Moreover, PA membrane transfer onto atomically flat substrate like Si is much simpler than onto relatively rough surfaces like ITO or FTO coated glass.…”

“…32 PA template assisted electrodeposition is a simple and cost effective method that gives dense, high aspect ratio, crystalline vertically standing 1D z E-mail: rnayak@amity.edu; ranunayakbose@gmail.com nanostructures. [33][34][35] It is observed that for successful electrochemical growth of nanowires/nanorods using PA template, removal of the barrier oxide is of prime importance. Two different techniques have been reported for the removal of barrier oxide layer from the bottom of the pore channels.…”

“…Most reliable way appears to be the use ordered self-organized through hole PA membrane on conductive substrates to grow uniform array of semiconductor nanowires. 33,35,38,39 However, PA template assisted growth of high aspect ratio semiconductor nanowires directly on transparent conductive oxides (TCO) has not been reported. Rather, a thin metal coating is electrodeposited prior, for ease and faster rate of semiconductor deposition.…”

“…Some major modifications and thus significant improvements have been incorporated in comparison to the already reported literatures on transfer and adhesion of PA membrane to enable the growth of high aspect ratio, vertically standing CdTe nanowires on FTO coated glass. 33,35,39 …”

Nanoarchitectured Array Electrodes for Rechargeable Lithium‐ and Sodium‐Ion Batteries

“…By changing the anodization time, the pore length can be tuned from several tens of nanometers to several tens of micrometers. It should be emphasized that the high controllability of the geometric parameters of the AAO template results in the high controllability of the resulting arrays since the formed solid product inside the pores replicates the shape of the void space in the template . Harsh conditions such as acidic or alkaline etching are usually required to remove the AAO membrane.…”