Failure physics of integrated circuits and relationship to reliability

Stojadinović, N.; Ristić, S. D.

doi:10.1002/pssa.2210750102

Cited by 6 publications

(1 citation statement)

References 38 publications

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“…Next to mechanical fragility, this results in higher electrical resistance, so an increase in noise. To compensate the decrease in signal-to-noise ratio, higher current densities are required, leading to electromigration (Pierce and Brusius, 1997) and electrical over-stress(EOS) (Stojadinovic and Ristic, 1983).…”

Section: Introductionmentioning

confidence: 99%

Batch fabricated scanning Hall probes by corner lithography

Hatakeyama¹

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In this chapter, I discuss nanometer sized Hall crosses on cantilever probes, fabricated by means of corner lithography. Scanning attempts on a permanent magnet show a strong topographic cross-talk. As this cross-talk was three orders of magnitude larger than the expected Hall signal, magnetic imaging over such a rough surface was impossible. We investigated the origin of the cross-talk by four different methods. These measurements clearly show that the asymmetry in the Hall cross, caused by fabrication imperfections, leads to an extra series resistance between the voltage sensing leads, resulting in an offset voltage on top of the output signal. Since this additional resistance is temperature dependent, the offset voltage varies with probe temperature. As the probe is heated by Joule heating, its temperature varies with probe-sample distance. This distance is slightly modulated due to topography of the sample while scanning, resulting in the observed strong topographic cross-talk. This work is a team effort by Edin Saraijlic, Martin Siekman and myself. My contribution is the theoretical model, the experiments and their analysis. The scanning Hall probes were fabricated by Edin Sarajlic. Martin Siekman assisted in construction of the measurement setup.

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Section: Introductionmentioning

confidence: 99%

Batch fabricated scanning Hall probes by corner lithography

Hatakeyama¹

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Reliability of n-channel and p-channel MOSTs in CMOS integrated circuits

Stojadinović

Dimitrijev²,

Mijalković

et al. 1983

Phys. Stat. Sol. (a)

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The reliability of n‐channel and p‐channel MOSTs in CMOS (complementary MOS) integrated circuits is investigated applying bias—temperature aging test. It is evidenced that negative bias—temperature aging causes p‐channel MOST threshold voltage increase and n‐channel MOST threshold voltage decrease, while positive bias—temperature aging causes p‐channel MOST threshold voltage decrease and n‐channel MOST threshold voltage increase. The causes of the observed threshold voltage instabilities are probably electron injection into the gate oxide for positive bias—temperature aging and hole and Si‐ion injection for negative bias—temperature aging. Bias—temperature aging test also results in 16.6% of investigated MOSTs to failure suddenly that being the consequence of gate/p+—drain (5%), gate/n−—substrate (2.5%), and gate/p‐well (5.8%) shorts and gate opens (3.3%).

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Characteristics with negative differential resistance of a device using a Si-Sio2 structure

Tien¹

1985

phys. stat. sol. (a)

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Failure physics of integrated circuits and relationship to reliability

Cited by 6 publications

References 38 publications

Batch fabricated scanning Hall probes by corner lithography

Batch fabricated scanning Hall probes by corner lithography

Reliability of n-channel and p-channel MOSTs in CMOS integrated circuits

Characteristics with negative differential resistance of a device using a Si-Sio2 structure

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