Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

Gaj, Kris; Homsirikamol, Ekawat; Rogawski, Marcin

doi:10.1007/978-3-642-15031-9_18

Cited by 49 publications

(29 citation statements)

References 6 publications

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“…12. Evaluation of SF algorithm on FPGA was carried out on certain well know parameters used by various authors [10], [11], [12], [13], [14], [15] for the assessment of the performance of their proposed FPGA based designs. A brief description of the design evaluation parameters of SF implementation are mentioned below.…”

Section: Substitution Box (S-box)mentioning

confidence: 99%

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

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Abstract-Field-Programmable Gate Arrays (FPGAs) have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF) shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loopunroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

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Section: Substitution Box (S-box)mentioning

confidence: 99%

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Khan¹,

Ibrahim²,

Ebrahim³

et al. 2015

IJCNIS

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“…There exist several Keccak implementations where most of them have been designed for FPGAs. Highspeed implementations have been reported by J. Strömbergson [39], B. Baldwin et al [3], E. Homsirikamol et al [22], K. Kobayashi et al [31], F. Gürkaynak et al [20], and K. Gaj et al [16,17]. Low-area FPGA designs have been presented by S. Kerckhof et al [29], J.-P. Kaps et al [26], and B. Jungk and J. Apfelbeck [25].…”

Section: Hash Functions For Rfidmentioning

confidence: 99%

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Pessl

Hutter

2013

Cryptographic Hardware and Embedded Systems - CHES 2013

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Abstract. There exists a broad range of RFID protocols in literature that propose hash functions as cryptographic primitives. Since Keccak has been selected as the winner of the NIST SHA-3 competition in 2012, there is the question of how far we can push the limits of Keccak to fulfill the stringent requirements of passive low-cost RFID. In this paper, we address this question by presenting a hardware implementation of Keccak that aims for lowest power and lowest area. Our smallest (fullstate) design requires only 2 927 GEs (for designs with external memory available) and 5 522 GEs (total size including memory). It has a power consumption of 12.5 µW at 1 MHz on a low leakage 130 nm CMOS process technology. As a result, we provide a design that needs 40 % less resources than related work. Our design is even smaller than the smallest SHA-1 and SHA-2 implementations.

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“…The SHA-2 algorithm replaced the SHA-1, which had been in use since 1995. Until now, many architectures, for efficient VLSI realization of SHA-2 algorithm, have been proposed and their performance have been evaluated by using ASIC libraries and FPGA [2][3][4][5][6][7][8][9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2

Mestiri¹,

Kahri²,

Bouallègue³

et al. 2014

IJCNIS

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Abstract-The Hash function has been studied by designers with the goal to improve its performances in terms of area, frequency and throughput. The Hash function is used in many embedded systems to provide security. It is become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and SHA-512 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieves good performance in term of area, frequency and throughput.

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Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

Cited by 49 publications

References 6 publications

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

FPGA Implementation of Secure Force (64-Bit) Low Complexity Encryption Algorithm

Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID

Efficient FPGA Hardware Implementation of Secure Hash Function SHA-2

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