Fair cache sharing and partitioning in a chip multiprocessor architecture

Kim, Seongbeom; Chandra, D.; Solihin, Yan

doi:10.1109/pact.2004.1342546

Cited by 80 publications

(30 citation statements)

References 7 publications

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“…There has been a significant amount of work on dynamic cache partitioning (DCP) [2,11,12]. The DCP scheme dynamically partitions the cache (shared by the parallel threads) in such a way that the impact of the cache replacement policy and its direct impact on the relative speed of each thread leads to load balance.…”

Section: Experimental Evaluationmentioning

confidence: 99%

“…The DCP scheme dynamically partitions the cache (shared by the parallel threads) in such a way that the impact of the cache replacement policy and its direct impact on the relative speed of each thread leads to load balance. In [11,12] the authors' work focus on issues such as fairness, throughput, or ensuring a minimum performance for an application. Sai P.M., et al [2] proposed a dynamic intra-application cache partitioning scheme to improve the performance of parallel programs by speeding up the slower threads during the runtime.…”

Section: Experimental Evaluationmentioning

confidence: 99%

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Dynamic Cache Reservation to Maximize Efficiency in Shared Cache Multicores

Wang

Liu

et al. 2011

2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control

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Extracting performance from modern multicore architectures requires that parallel sections be divided into many threads of execution. In order to fully utilize these threads effectively, load balancing has become one of the most important factors that affect the performance of applications on multicores. In this paper, we have shown that the threads that belong to a single, multithreaded application can exhibit a poorly balancing performance. We propose a dynamic cache reservation scheme which can redistribute the reserved cache space to the critical thread for speeding up during the applications running. In our implementation, we balance performance of these threads belonging to the same application based on runtime information. Our experimental evaluation indicates that, the proposed dynamic cache reservation yields benefits up to 21% over a shared cache without cache reservation, up to 6% over a statically partitioned cache scheme.

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Section: Experimental Evaluationmentioning

confidence: 99%

Section: Experimental Evaluationmentioning

confidence: 99%

Dynamic Cache Reservation to Maximize Efficiency in Shared Cache Multicores

Wang

Liu

et al. 2011

2011 First International Conference on Instrumentation, Measurement, Computer, Communication and Control

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show abstract

“…Chip multi-processor (CMP) has become the most common processor in the current cluster and desktop computer, and it is also the current development direction [1,2]. A great deal of work is directed at the scheduling of on-chip processors in an effort to improve program performance and system resource utilization.…”

Section: Introductionmentioning

confidence: 99%

Improving co-running program’s performance on CMP

Tian

Li²,

Niu³

et al. 2017

MATEC Web Conf.

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Abstract. Chip multi-processor (CMP) has become the most common processor in the current cluster and desktop computer, and it is also the current development direction. On CMP, programs usually co-running with each other. However, programs commonly interfere with each other. Some time the interference takes big effect, which cause serious drop down of performance. In order to avoid the serious performance interference, programs should be scheduled reasonably to different socket to improve the program's performance and system's utilization. In this paper we propose a new scheduling method to realize a more reasonable scheduling. We do not only consider the LLC miss rate, but also consider the LLC reference of the programs. By the information of LLC reference and LLC miss rate, we schedule programs to different sockets, which realize a reasonable scheduling. The experiment result show that making use of the scheduling method proposed by our paper, program's performance can improve 4%, because the performance improve is realized by on-chip resource, which is a big contribution.

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“…With the development of integrated circuit technology, chip multi-processor (CMP) has become the most common processor in the current cluster and desktop computer, and it is also the current development direction [1,2].…”

Section: Introductionmentioning

confidence: 99%

Ensuring the Fairness of program’s performance on CMP

Wang¹,

Gao²,

Hou³

et al. 2017

MATEC Web Conf.

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Abstract. On CMP, programs commonly interference with each other. But for programs co-running on CMP, serious performance dropdown is not expected. With the growth of the program's size, program's contention for limited shared resources in the system will become increasingly intense, and the resulting impact on system performance will be even more pronounced. How to allocate and share limited shared resources among programs is a very important problem. In this paper we propose a new method to ensure the fairness of program's performance on CMP. The share resource CPU and memory are included in our study. Meanwhile, the Linux resource management tool Cgroups is used to realize our idea. By the resource we profiled and the tool support, we realize a reasonable resource dividing method to ensure the fairness of program's performance. The reasonable resource dividing method include three Engine. The experiment result show that making use of the fairness resource dividing method proposed by our paper, compared with operating system scheduling, program's performance difference can be largely reduced.

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Fair cache sharing and partitioning in a chip multiprocessor architecture

Cited by 80 publications

References 7 publications

Dynamic Cache Reservation to Maximize Efficiency in Shared Cache Multicores

Dynamic Cache Reservation to Maximize Efficiency in Shared Cache Multicores

Improving co-running program’s performance on CMP

Ensuring the Fairness of program’s performance on CMP

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