Falcon — A Flexible Architecture For Accelerating Cryptography

Kiningham, Kevin; Levis, Philip; Anderson, Mark S.; Boneh, Dan; Horowitz, Mark; Shih, Maurice

doi:10.1109/mass.2019.00025

Cited by 9 publications

(8 citation statements)

References 14 publications

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“…Crystals-Dilithium is one of the three digital signature schemes selected for the NIST standardization with Falcon [7] and SPHINCS+ [8]. The parameter sets of Dilithium are reported in Table 2; columns pk and sign indicate the size in bytes of the public key and signature respectively.…”

Section: B Crystals-dilithiummentioning

confidence: 99%

“…The National Institute of Standards and Technology (NIST) started the PQC Standardization Process in 2016, and 69 algorithms were submitted in 2017 for KEM and digital signature. In the first round of standardization (on July 2022) CRYSTALS-Dilithium [6], Falcon [7], and SPHINCS+ [8] were selected for digital signature and CRYSTALS-Kyber [9] was selected for KEM. Among the standardized algorithms, CRYSTALS-Kyber and CRYSTALS-Dilithium showed several synergies since both are based on the hardness of the Module Learning With Errors (MLWE) problem.…”

Section: Introductionmentioning

confidence: 99%

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CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms

Matteo,

Sarno,

Saponara

2024

IEEE Access

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This paper presents the design and FPGA implementation of a hardware accelerator for the Post-Quantum CRYSTALS-Kyber and CRYSTALS-Dilithium algorithms, named CRYPHTOR (CRYstals Polynomial HW acceleraTOR). The proposed architecture includes a unified memory arrangement and dedicated ALUs for Kyber and Dilithium, capable of accelerating several polynomial operations such as Number Theoretic Transform (NTT), Inverse NTT, Coefficient-Wise Multiplication (CWM), modular addition and subtraction, modular reduction, and the multiply-accumulate operation. CRYPHTOR has been integrated into two SoCs: one based on a 64-bit RISC-V processor and the other on a 32-bit RISC-V microcontroller. In these configurations, up to 26x and 300x of speedup has been obtained for the NTT, and up to 30x and 140x of speedup for the matrix-vector multiplication compared to the software implementation running on the RISC-V processors.

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Section: B Crystals-dilithiummentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

CRYPHTOR: A Memory-Unified NTT-Based Hardware Accelerator for Post-Quantum CRYSTALS Algorithms

Matteo,

Sarno,

Saponara

2024

IEEE Access

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“…Cryptographic Primitives. References: Stoffelen2019 [98], Kiningham2019 [88], Campos2020 [97], Roy2020 [96], Saarinen2020 [87], Jager2020 [90], Loiseau2018 [91]. the instruction set architecture (ISA) with new function-based primitives, thereby improving the robustness of the software in terms of security.…”

Section: Reduce Attack Surfacementioning

confidence: 99%

“…Fixed function hardware accelerators such as an AES engine cannot support new ciphers. Kiningham et al [88] introduce Falcon, a hardware architecture used to accelerate various ciphers on energy-constrained devices. Falcon provides a general execution engine that support bitslice and permutation instructions, which are the backbone operations of current and probably future dominant ciphers including AES, Cha-Cha, SHA-256, RSA, Curve25519 ECC, and post-quantum cryptography such as R-LWE.…”

Section: Symmetric and Asymmetric Cryptographymentioning

confidence: 99%

“…European Processor Initiative (EPI), one of the cornerstones of the EuroHPC Joint Undertaking, a new European Union strategic entity focused on pooling the Union's and national resources on HPC to build and deploy the most powerful supercomputers within Europe, is preparing to adopt RISC-V as its core solution for exascale embedded HPC platform [9]. protection [54,56,57,59,61,[69][70][71][72], ISA security extensions [66,67,[73][74][75][76][77][78][79][80][81][82][83][84], cryptographic engines and primitives [78][79][80][81][82][83][85][86][87][88][89][90][91][92][93][94][95][96][97][98], and side-channel prevention [99][100][101]…”

Section: Introductionmentioning

confidence: 99%

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A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

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