False write through and un-restored write electrical level fault models for SRAMs

Adams, R.D.; Cooley, E.S.

doi:10.1109/mtdt.1997.619391

Cited by 32 publications

(10 citation statements)

References 6 publications

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“…They cause mainly time-related faults referred to as dynamic faults. Dynamic faults are divided into three types: (a) Dynamic Memory Cell Array Faults [6], [19], [20] (b) Dynamic/Delay Address Decoder Faults [3], [4], [5], [7] and (c) Dynamic Peripheral Circuit Faults [21], [22].…”

Section: Dynamic Testsmentioning

confidence: 99%

BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

Hamdioui

Al-Ars

Jiménez³

et al. 2008

2008 2nd International Conference on Signals, Circuits and Systems

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The continued increase of the integration density of systems on chip (SoCs) and the number of embedded memory blocks in them, together with the continued technology scaling, increases their sensitivity to a variety of potential manufacturing (new) defects. Standard march tests are usually used to achieve a good fault/defect coverage. This paper presents an experiment in diagnosing defects in the circuitry responsible for the realization of bit, byte or group write enable in memories. First defects in such circuitry are analyzed, and fault models together with an appropriate test algorithm are presented. Subsequently, the test is added to an existing BIST engine to target the bit/byte write enable faults. The preliminary silicon results of two experiments are presented. They validate some of the targeted fault models and show the importance of considering bit/byte write enable faults for high outgoing product quality.

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Section: Dynamic Testsmentioning

confidence: 99%

BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

Hamdioui

Al-Ars

Jiménez³

et al. 2008

2008 2nd International Conference on Signals, Circuits and Systems

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“…The two fault models, relative to defects Df1 and Df5 are URWF and URRF [Ada97]. Their definitions are the following: …”

Section: Df5mentioning

confidence: 99%

“…Among these, we consider the test pattern proposed in [Ada97,Nig98]. We have shown in the previous sections that the URWF detection requires writing a certain data D in a cell and reading its complementary value D exactly during the next memory access in another cell belong the same pair of bit line.…”

Section: Existing Test Solution For Urwfsmentioning

confidence: 99%

“…We have shown in the previous sections that the URWF detection requires writing a certain data D in a cell and reading its complementary value D exactly during the next memory access in another cell belong the same pair of bit line. The March-like test proposed in [Ada97,Nig98] has complexity 5N and is a particular implementation of March MATS+ (see Figure 9). The first element M 0 operates a w0 on all the cells of the memory.…”

Section: Existing Test Solution For Urwfsmentioning

confidence: 99%

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Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

et al. 2007

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In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more effective in terms of resistive defect detection than that of URRFs and we list the necessary test conditions to detect them.Keywords: Memory testing, dynamic faults, resistive-open defects, pre-charge circuits. Corresponding author

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“…A lot of work has been done on investigating resistive defects [1], [9], [5], [10], [7] but without considering the presence of parasitic components of the defective node. Some work also has been done on establishing the presence of parasitic memory effect in CMOS logic and SRAMs [11], [6].…”

Section: Introductionmentioning

confidence: 99%

Influence of parasitic memory effect on single-cell faults in SRAMs

Irobi

Al-Ars

Hamdioui

et al. 2011

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems

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Parasitic node capacitance and faulty node voltage of a defective node can induce serious parasitic effects on the electrical behavior of SRAMs. This paper evaluates the impact of parasitic memory effect on the detection of single-cell faults in SRAMs. It demonstrates that detection is significantly influenced by parasitic node components; something that is often not accounted for during memory testing. Finally, it shows the impact of parasitic node components on all possible opens in the SRAM memory cell array, using node voltages from GND to VDD.Index Terms-Parasitic memory effect, static faults, SRAMs.

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False write through and un-restored write electrical level fault models for SRAMs

Cited by 32 publications

References 6 publications

BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

BIST enhancement for detecting bit/byte write enable faults in SOC SRAMs

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

Influence of parasitic memory effect on single-cell faults in SRAMs

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