Fan-out enabled spin wave majority gate

Mahmoud, Abdulqader; Vanderveken, Frederic; Adelmann, Christoph; Ciubotaru, Florin; Hamdioui, Said; Cotofana, Sorin

doi:10.1063/1.5134690

Cited by 49 publications

(60 citation statements)

References 34 publications

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“…Many existing options can be used for the excitation and detection cells, e.g., microstrip antennas 7,28,30 , magnetoelectric cells 7,31-33 , spin orbit torques 7,34,35 . In contrast to the ladder shape structure 22 , the proposed triangle shape structure doesn't need the replication of one of its inputs to enable fanout capability and thus is more energy efficient as will be demonstrated in the performance evaluation subsection (Subsection IV D).…”

Section: A Proposed Fo2 Sw Majority Gatementioning

confidence: 99%

“…On the other hand, when comparing with the SW Majority gate 22 , the proposed triangle shape Majority structure saves 25% energy while keeping the same delay. Also, the proposed XOR structure saves 50% energy while keeping the same delay when compared with the SW XOR gate in 22,23 . This is because of the fact that extra ME cells are required to enable the fanout capability in 22,23 .…”

Section: Performance Evaluationmentioning

confidence: 99%

“…This is because of the fact that extra ME cells are required to enable the fanout capability in 22,23 . We also note that, for proper gate operation in the ladder shape structure 22,23 , inputs may have to be excited at different energy levels depending on whether they have a straight path to the outputs or face bent regions at the edges. In contrast, the proposed triangle shape structure doesn't require an extra ME cell to achieve the fanout capability, which saves energy and allows for equal energy inputs excitation.…”

Section: Performance Evaluationmentioning

confidence: 99%

See 2 more Smart Citations

Fanout of 2 Triangle Shape Spin Wave Logic Gates

Mahmoud¹,

Vanderveken²,

Ciubotaru³

et al. 2021

Preprint

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Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave logic gates, and 16nm and 7nm CMOS. The results demonstrate that the proposed structures provide energy reduction of 25%-50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction between 43x and 0.8x when compared to the 16nm and 7nm CMOS while having delay overhead between 11x and 40x.

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Section: A Proposed Fo2 Sw Majority Gatementioning

confidence: 99%

Section: Performance Evaluationmentioning

confidence: 99%

Section: Performance Evaluationmentioning

confidence: 99%

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Fanout of 2 Triangle Shape Spin Wave Logic Gates

Mahmoud¹,

Vanderveken²,

Ciubotaru³

et al. 2021

Preprint

Self Cite

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“…Research on SW technology based logic and circuit designs is in early stage. At the logic/gate level, some basic single output gates (such as NOT, (N)AND, (N)OR, and X(N)OR) were reported in [8]- [10], while some multi-output gates were discussed in [11]- [13]. At the circuit level, dedicated operators for neuromorphic applications were developed in [14], [15]; examples are upper and lower threshold operators, truncated difference operators, literal operators, cyclic operators and minimum and maximum operators.…”

Section: Introductionmentioning

confidence: 99%

Spin Wave Based Full Adder

Mahmoud

Vanderveken

Ciubotaru

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of 1 Majority and 2 XOR gates, which outputs Sum and Carry − out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22 nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22 nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.

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“…Different spin wave logic gates have already been demonstrated [9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] . The first experimental spin wave logic gate was designed based on the Mach-Zender interferometer 9 .…”

Section: Introductionmentioning

confidence: 99%

4-output Programmable Spin Wave Logic Gate

Mahmoud

Vanderveken

Adelmann

et al. 2020

2020 IEEE 38th International Conference on Computer Design (ICCD)

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To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set {AND, NAND, OR, NOR, XOR, and XNOR} . Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16 nm CMOS counterparts.The results indicate that for the same functionality, our approach provides 3× and 16× energy reduction, when compared with conventional SW and 16 nm CMOS implementations, respectively.

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Fan-out enabled spin wave majority gate

Cited by 49 publications

References 34 publications

Fanout of 2 Triangle Shape Spin Wave Logic Gates

Fanout of 2 Triangle Shape Spin Wave Logic Gates

Spin Wave Based Full Adder

4-output Programmable Spin Wave Logic Gate

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