FANS: FPGA-Accelerated Near-Storage Sorting

Qiao, Weikang; Oh, Jihun; Guo, Licheng; Chang, M.F.; Cong, Jason

doi:10.1109/fccm51124.2021.00020

Cited by 17 publications

(7 citation statements)

References 16 publications

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“…The merge tree sorting algorithm is favored for FPGA-based sorters due to its massive data parallelism, less control overhead and regular memory access patterns [1], [2], [3], [4], [5], [6], [7], [8], [9]. In this section, we first introduce the HBM-based FPGAs.…”

Section: Background Reviewmentioning

confidence: 99%

“…But if the remaining resources only allow us to build a final merge tree whose throughput is equal to the bandwidth of a single channel, then the overall sorting performance will be limited by the final merge, no matter how much better the memory bandwidth utilization we achieve in phase 1. One may wonder if we can reprogram the FPGA in phase 2 to have a wider tree for final merging, but the reprogramming overhead takes several seconds [9] and thus is not practical in this case.…”

Section: Two Phases In Topsortmentioning

confidence: 99%

“…TopSort is an in-memory sorter [29], which stores the entire input in main memory such as an HBM or a DRAM. An inmemory sorter has much higher overall sorting performance than an in-storage sorter, which requires a second-level storage such as SSD to sort a larger dataset and thus is bounded by the slow I/O [5], [9]. In fairness, we compare TopSort against several CPU and FPGA in-memory sorters here.…”

Section: Comparison With State-of-the-art Cpu and Fpga Sortersmentioning

confidence: 99%

“…Sorting is one of the fundamental computation kernels in many big data applications and there have been continuous efforts on designing high-performance sorting accelerators on FPGAs [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15]. Most of these sorting accelerators are based on the multi-way merge tree sort algorithm [1], [2], [3], [4], [5], [6], [7], [8], [9], due to its massive data parallelism and regular memory access patterns. Before the maturing of the high-bandwidth memory (HBM) technology, these sorters were usually implemented on DRAM-based FPGAs and bounded by the off-chip memory bandwidth [7], [8].…”

Section: Introductionmentioning

confidence: 99%

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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Qiao¹,

Guo²,

Fang³

et al. 2022

Preprint

Self Cite

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The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth, as the required on-chip resource usage grows at a much faster rate and would bound the sorting performance in turn. Second, designers need an in-depth understanding of HBM's characteristics to effectively utilize the HBM bandwidth. To tackle these challenges, we present TopSort, a novel two-phase sorting solution optimized for HBM-based FPGAs. In the first phase, 16 merge trees work in parallel to fully utilize 32 HBM channels' bandwidth. In the second phase, TopSort reuses the logic from phase one to form a wider merge tree to merge the partially sorted results from phase one. TopSort also adopts HBM-specific optimizations to reduce resource overhead and improve bandwidth utilization. TopSort can sort up to 4 GB data using all 32 HBM channels, with an overall sorting performance of 15.6 GB/s. TopSort is 6.7× and 2.2× faster than state-of-the-art CPU and FPGA sorters.

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Section: Background Reviewmentioning

confidence: 99%

Section: Two Phases In Topsortmentioning

confidence: 99%

Section: Comparison With State-of-the-art Cpu and Fpga Sortersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs

Qiao¹,

Guo²,

Fang³

et al. 2022

Preprint

Self Cite

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“…Their accelerator utilizes an NVMe lash drive with an onboard FPGA chip. The authors in [51] propose FANS; an FPGA accelerated near-storage sorting system. Their system is able to sort hundreds of gigabytes of data on a single Samsung SmartSSD.…”

Section: Introductionmentioning

confidence: 99%

Sorting in Memristive Memory

Alam

Najafi

TaheriNejad

2022

J. Emerg. Technol. Comput. Syst.

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Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the first architectures for in-memory sorting of data to the best of our knowledge. We propose two architectures. The first architecture is applicable to the conventional format of representing data, i.e., weighted binary radix. The second architecture is proposed for developing unary processing systems, where data is encoded as uniform unary bit-streams. As we present, each of the two architectures has different advantages and disadvantages, making one or the other more suitable for a specific application. However, the common property of both is a significant reduction in the processing time compared to prior sorting designs. Our evaluations show on average 37 × and 138 × energy reduction for binary and unary designs, respectively, compared to conventional CMOS off-memory sorting systems in a 45nm technology. We designed a 3 × 3 and a 5 × 5 Median filter using the proposed sorting solutions, which we used for processing 64 × 64 pixel images. Our results show a reduction of 14 × and 634 × in energy and latency, respectively, with the proposed binary, and 5.6 × and 152 × 10 3 in energy and latency with the proposed unary approach compared to those of the off-memory binary and unary designs for the 3 × 3 Median filtering system.

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