FAReP: Fragmentation-Aware Replacement Policy for Task Reuse on Reconfigurable FPGAs

R3TOS-Based Integrated Modular Space Avionics for On-Board Real-Time Data Processing

“…The aim of the fragmentation metric is to address the limitation in heterogeneous FPGAs where matching locations for tasks are not guaranteed to be found at the border of existing placements or the border of the chip as is the case on homogenous FPGAs. This was reported as part of [23]. In addition, a technique called Expanding the unusable Area Scheme (EUAS) is also presented to further improve chip area utilization and to circumvent the creation of unusable areas due to the heterogeneous nature of the chip is also presented and reported in [21].…”

“…The second contribution of this thesis is the presentation of a task reuse mechanism on COTS FPGAs to circumvent their large reconfiguration overhead in runtime applications [22]. The reuse mechanism is based on a novel replacement policy which not only aim to preserve tasks with large configuration overhead on the chip, but also uses each task replacement window to offer some defragmentation of the FPGA area [23].…”

“…On the other hand, task reuse is aimed at reducing the number of hardware tasks configuration. This is achieved by retaining carefully selected tasks on the chips even after their computation, such that if they are required again in the future, their configuration will be circumvented [38] [23]. This means that the cumulative occupancy of the configuration port is reduced, making it more available for other critical operations [22], while also avoiding frequent external memory access.…”

“…As pointed out in chapter 3, many state-of-the-art techniques for computing fragmentation such as the adjacency [63] or vertex based heuristics [71] do not suit a heterogeneous chip (which is the target in this thesis). This is because tasks' location on heterogeneous chips have definite start and end points which, often, do not fall at the border of existing placements [23]. The approach proposed in this sub-section, is based on computing the degree of isolation (as well as the adjacencyif it exists) of the possible location area (to be) occupied by task(s).…”

A Survey: FPGA‐Based Dynamic Scheduling of Hardware Tasks

“…Table 1 (Refs. [15,16,18–22,25–42,45–49,51–55,57–70]) lists the research work done by researchers for different optimization goals in each time period. During the period 20002005, 9 papers were published.…”