Fast, Accurate and Detailed NoC Simulations

Abstract

Network -on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed. Cycle and bit accurate simulation is necessary when the actual router's RTL description needs to be evaluated and verified. However, extensive simulation of the NoC architecture with cycle and bit accuracy is prohibitively time consuming. In this paper we describe a simulation method to simulate large parallel homogeneous and heterogeneous network-on-chips on a single FPGA. The method is especially suitable for parallel systems where lengthy cycle and bit accurate simulations are required. As a case study, we use a NoC that was modelled and simulated in SystemC. We simulate the same NoC on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the Sys-temC simulation we achieved a speed-up of 80-300, without compromising the cycle and bit level accuracy.

Fast scalable FPGA-based Network-on-Chip simulation models

“…As has been shown in previous work [5], [6], time-multiplexing in the context of network simulation requires special care to retain proper ordering of events and careful state management to ensure that all routers in the network have a consistent view of the system. For instance, within a single target cycle, a router might send traffic to routers that were simulated in previous host cycles, but also send traffic to routers that will be simulated in subsequent host cycles.…”

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip

“…Assume that the voltage generator be operated in case of switching the logic level from 1 to 0 and from 0 to 1. There are six modes, from (1) to (6). At the mode (1) and (4), the generator is at stable condition which is before and after transition.…”

“…Asynchronous NoC architecture has potential advantages such as low-power consumption maintaining total performance [1]- [6]. An asynchronous routing is suitable for a many-core processing system which consists of processing elements (PEs) and communication links.…”

An Area Optimized Robust Router Design Implementation

“…data [1] An Area Optimized Robust Router Design Implementation the data. RS-232 and other asynchronous protocols do not use a clock pulse, but the data must be timed very accurately.…”