Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance

Függer, Matthias; Kinali, Attila; Lenzen, Christoph; Wiederhake, Ben

doi:10.1109/async.2018.00025

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…Obvious examples of such control loops are clock synchronization circuits, but MC has been shown to be useful for adaptive voltage control [13] and fast routing with an acceptable low probability of data corruption [29] as well. This type of application suggests to explore whether efficient circuits exist for a wider range of arithmetic operations, like e.g.…”

Section: Discussionmentioning

confidence: 99%

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

Bund

Lenzen

Medina

2020

IEEE Trans. Comput.

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Friedrichs et al. (TC 2018) showed that metastability can be contained when sorting inputs arising from time-to-digital converters, i.e., measurement values can be correctly sorted without resolving metastability using synchronizers first. However, this work left open whether this can be done by small circuits. We show that this is indeed possible, by providing a circuit that sorts Gray code inputs (possibly containing a metastable bit) and has asymptotically optimal depth and size. Our solution utilizes the parallel prefix computation (PPC) framework (JACM 1980). We improve this construction by bounding its fan-out by an arbitrary f ≥ 3, without affecting depth and increasing circuit size by a small constant factor only. Thus, we obtain the first PPC circuits with asymptotically optimal size, constant fan-out, and optimal depth. To show that applying the PPC framework to the sorting task is feasible, we prove that the latter can, despite potential metastability, be decomposed such that the core operation is associative. We obtain asymptotically optimal metastability-containing sorting networks. We complement these results with simulations, independently verifying the correctness as well as small size and delay of our circuits.

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Section: Discussionmentioning

confidence: 99%

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

Bund

Lenzen

Medina

2020

IEEE Trans. Comput.

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“…Several approaches [20,21] have been proposed specifically to tackle frequency peaking, as this is often an issue in fast-locking PLL systems [22] due to the timing constraint of critical paths previously stated. These approaches usually involve multiple PLLs, and therefore suffer from diminished stability due to asynchronous switching between the outputs of the component PLLs [23].…”

Section: Introductionmentioning

confidence: 99%

A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

Cheong

Kim²

2021

IEEE Access

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This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phaseshifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the feedback and reference signals becomes sufficiently small. Then, a toggling phase-shifting in the second stage achieves further reduction of the phase offset by delaying the feedback and reference signals. A subsequent adaptive target index-shifting stage then detects fine-locking in frequency and rapidly performs phase-locking to the present phase of the feedback signal instead of the initial target phase. This TSPS-ADPLL avoids frequency peaking by choosing oscillator control codes that generate frequencies below or near the target. Fabricated in a 28nm CMOS process, this ADPLL can lock within 1.0s, producing a 2.4GHz output clock without frequency peaking. It has an RMS jitter of 2.53ps and draws 2.89mW from a 1.0V supply.INDEX TERMS Fast-locking, phase-shifting, frequency peaking, frequency search, digital clock generator, all-digital phase-locked loop (ADPLL).

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PALS: Plesiochronous and Locally Synchronous Systems

Bund

Függer

Lenzen

et al. 2020

2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

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Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: (i) by deriving it from a single, central clock source, (ii) by local, free-running oscillators, or (iii) by handshaking between neighboring modules.Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or fully asynchronous, suggesting that the designer's choice is limited to deciding where to draw the line between synchronous and asynchronous design.In contrast, we take the view that the better question to ask is how synchronous the system can and should be. Based on a distributed clock synchronization algorithm, we present a novel design providing modules with local clocks whose frequency bounds are almost as good as those of corresponding free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15 nm ASIC implementation running at 2 GHz yield mathematical worst-case bounds of 30 ps on phase offset for a 32 × 32 node grid network.

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Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance

Cited by 4 publications

References 20 publications

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

Optimal Metastability-Containing Sorting via Parallel Prefix Computation

A Fast-Locking All-Digital PLL With Triple-Stage Phase-Shifting

PALS: Plesiochronous and Locally Synchronous Systems

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