Fast and accurate electro-thermal analysis of three-dimensional power delivery networks

Todri‐Sanial, Aida; Bosio, Alberto; Dilillo, Luigi; Girard, Patrick; Virazel, Arnaud

doi:10.1109/eurosime.2013.6529956

Cited by 2 publications

(1 citation statement)

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“…The tiers next to package have some of the heat alleviated due to the secondary heat flow path from die to package, whereas the middle tiers tend to experience higher temperature gradients. TSVs conduct the electrical connections between tiers but also transfer heat from a hot to a cooler tier, hence contributing to nonuniform thermal gradients in a tier and between tiers [7], [8]. The heat transfer between the tiers creates thermal wave zones around the TSVs, and hot spots can be created on the overlapping of these waves, which can detrimentally impact the performance of devices and parasitics of interconnects and eventually lead to Joule heating phenomenon [8].…”

Section: Introductionmentioning

confidence: 99%

A Study of 3-D Power Delivery Networks With Multiple Clock Domains

Todri‐Sanial

Cheng

2016

IEEE Trans. VLSI Syst.

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Ongoing advancements in 3-D manufacturing are enabling 3-D ICs to contain several processing cores, hardware accelerators, and dedicated peripherals. Most of these functional units operate with independent clock frequencies for power management reasons or simply for being hard intellectual properties. Thus, as diverse and heterogeneous circuits can be implemented on a 3-D IC, it also leads to the use of multiple clock domains. While these domains allow many functional units to run in parallel to exploit 3-D potentials, they also introduce power delivery challenges. This paper proposes an efficient analysis for assessing the worst case power supply noise on 3-D power delivery networks (PDNs) with multiple clock domains. This paper discusses power and thermal integrity issues that arise from multiple clock domains that share the same 3-D global PDN. We first examine power supply noise distribution on each tier and investigate scenarios that lead to worst case noise. Thermal analyses are also performed and heat distribution among clock domains and tiers is examined. In addition, the impact of clock domain structure and frequency on the overall power supply noise and temperature distribution has been quantified. Experiments show that the multiclock domains can induce excessive noise and the through-silicon-vias can contribute to power supply noise and heat transfer among tiers. This paper presents a summary of guidelines for modeling, analyzing, and exploring a design of reliable 3-D PDNs with multiple clock domains.Index Terms-3-D ICs, clock networks, power and thermal integrity, power delivery networks (PDNs), through-siliconvias (TSVs).

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Section: Introductionmentioning

confidence: 99%