Fast and accurate lithography simulation using cluster analysis in resist model building

Kumar, Pardeep; Srinivasan, Babji; Mohapatra, Nihar R.

doi:10.1117/1.jmm.14.2.023506

Cited by 12 publications

(4 citation statements)

References 21 publications

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“…Most of the advanced fabrication teams are doing cross‐verification with another model to ensure no patterning defect escapes verification. Several physics‐based modelling has been developed for mask layout verification and yield prediction [63, 64].…”

Section: Computer‐aided Design (Cad) Analysis For Hotspot Detectionmentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

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Section: Computer‐aided Design (Cad) Analysis For Hotspot Detectionmentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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“…To select the appropriate combinations of critical patterns, several methods have been developed. [8][9][10][11][12][13][14][15][16][17] They can be categorized into three types of techniques roughly: dimension domain, parameter domain, and frequency domain.…”

Section: Introductionmentioning

confidence: 99%

“…4 Third, the patterns can be classified and selected based on their geometric characteristics, such as centroid, density, distribution, and connectivity. [8][9][10][11] However, the algorithm initialization has a significant impact on the efficacy of pattern classification outcomes. 8 Furthermore, the main approaches based on the parameter domain are as follows.…”

Section: Introductionmentioning

confidence: 99%

Selection approach of critical patterns for calibrating the physical resist model based on spectrum coverage

Wang,

Dong,

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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Background: The resist model is a significant element of computational lithography. Accurate calibration of the resist model is essential to obtain predictive results that closely match the exposure results on wafers. The trade-off between model accuracy and runtime is a challenging task. The selection of critical patterns used in model calibration affects these two metrics directly.Aim: Having a dependable method for choosing critical patterns during resist model calibration is essential for lithography engineers with diverse professional backgrounds. Equally important is the ability to decrease runtime while maintaining the precision of calibrated resist models. To address these concerns, we present an approach for selecting critical patterns utilized in resist model calibration.Approach: Since the spectrum carries pattern information, critical patterns are selected based on the coverage of the spectrum in the frequency domain. The spectrum coverage (SCO) of each pattern in the entire test pattern set is calculated according to the frequency and amplitude of all the spectra. Combinations of critical patterns are selected based on their SCO values. The optimal combinations include the most types of spectra and aim to adapt the calibrated model for broad applicability, encompassing both universal and unique patterns. Results:The model verification results are compared with the experience-based methods, which select critical patterns based on the pitch-to-CD ratio. The accuracy and effectiveness of the proposed methodology have been demonstrated through experimental results. Compared with experience-based methods that only have dense and isolated critical patterns, our proposed method has a 9.8% increase in accuracy and a 35% decrease in runtime. Even compared with experience-based methods that include forbidden pitches, our method still achieves a 6.4% increase in accuracy without increasing runtime.Conclusions: In summary, the suggested approach for selecting critical patterns based on SCO surpasses the experience-based methods in terms of both accuracy and efficiency. It can significantly shorten the modeling cycle of resists.

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“…Most of the advanced fabrication teams are doing cross verification with another model to ensure no patterning defect escapes verification. Several physics based modeling has been developed for mask layout verification and yield prediction [64][65][66].…”

Section: Model Based Layout Analysismentioning

confidence: 99%

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Vikram¹,

Agarwal

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Electrical Designs for Application SpecificIntegrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

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Fast and accurate lithography simulation using cluster analysis in resist model building

Cited by 12 publications

References 21 publications

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Selection approach of critical patterns for calibrating the physical resist model based on spectrum coverage

Critical Review of Current Trends in ASIC Writing and Layout Analysis

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