Fast and accurate resource estimation of RTL-based designs targeting FPGAS

Abstract

FPGAs have become complex, heterogeneous platforms targeting a multitude of different applications. Understanding how a design maps to them and consumes various FPGA resources can be difficult to predict, so typically designers are forced to run full synthesis on each iteration of the design. For complex designs that involve many iterations and optimizations, the run-time of synthesis can be quite prohibitive. In this paper, we describe a fast and accurate method of estimating the FPGA resources of any RTL-based design. We achieve run-times that are more than 60 times faster than synthesis and is on average within 22% of the actual mapped slices across a large benchmark suite targeting three different FPGA families. This resource estimator tool is first provided in Xilinx PlanAhead 10.1.

Optimising explicit finite difference option pricing for dynamic constant reconfiguration

“…µ and Var as in Equations 9, Skew = 0 and Kurt = 3 2: Calculate (α, β, γ): by solving Equation 10 3: Calculate Skew ′ , Kurt ′ : the skewness and kurtosis of the stencil using the standard statistical approach based on data points (f i+1,j−1 , f i+1,j , f i+1,j+1 ) and their corresponding probabilities (α, β, γ), an example is shown shown in Equation 13 and Equation 14 4: Calculate the difference between theoretical and stencil third and fourth order moments ε Skew , ε Kurt :…”

Mapping Loop Structures Onto Parametrized Hardware Pipelines

“…to operators in the library [6]. Such estimation tools are readily available in commercial software, such as Xilinx system generator [7] and PlanAhead [5]. The RTL resource estimation tool used by Xilinx is claimed to be 60 times faster than synthesis [5], which allows fast design space exploration.…”

“…Such estimation tools are readily available in commercial software, such as Xilinx system generator [7] and PlanAhead [5]. The RTL resource estimation tool used by Xilinx is claimed to be 60 times faster than synthesis [5], which allows fast design space exploration. Similar methods can be used to estimate the performance of the design by using a device-dependent library of delays for the estimated resources.…”

“…The common method used for resource estimation consists of identifying the basic operations in the algorithm, which can be represented as a data flow graph [4] or an RTL netlist [5]. A library of operators characterizing the device is then used to estimate the resources needed by the algorithm.…”

“…Therefore, we need a model of the design that facilitates estimating its parameters under speed and area constraints. Such area and speed estimation models are often applicationdependent [1], [3] or technology-dependent [4], [5].…”