Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs

Abstract

Abstract-Evolvable hardware may be considered as the result of a design methodology that employs an evolutionary algorithm to find an optimal solution to a given problem in the form of a digital circuit.Evolutionary algorithms typically require testing thousands of candidate solutions, taking long time to complete. It would be desirable to reduce this time to a few seconds for applications that require a fast adaptation to a problem. Also, it is important to consider architectures that may operate at high clock speeds in order to reach very speed-demanding situations.This paper presents an implementation on an FPGA of an evolvable hardware image filter based on a systolic array architecture that uses dynamic partial reconfiguration in order to change between different candidate solutions. The neighbor to neighbor connections of the array offer improved performance versus other approaches, like Cartesian Genetic Programming derived circuits. Time savings due to faster evaluation compensate the slower reconfiguration time compared with virtual reconfiguration approaches, but, at any rate, reconfiguration time has been improved also by reducing the elements to reconfigure to just the LUT contents of the configurable blocks.The techniques presented in this paper lead to circuits that may operate at up to 500 MHz (in a Virtex-5), filtering 500 megapixels per second, the processing element size of the array is reduced to 2 CLBs, and over 80 000 evaluations per second in a multiplearray structure in an FPGA permit to obtain good quality filters in around 3 seconds of evolution time.

On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

“…For this purpose, a specific use case-an EHW-based image filtering application-has been studied, using both topologies at different sizes and analyzing the performance of the resulting solutions. This use case has been chosen due to its extensive use in previous work [21,39,5,31,25]; nevertheless, the conclusions obtained for this use case are expected to be extensible to other applications.…”

Hexarray: A Novel Self-Reconfigurable Hardware System

“…virtual reconfiguration circuit (VRC) or native reconfiguration (often called dynamic partial reconfiguration, DPR), as shown in figure 2.2; additionally, a comparison is presented in Figure 2.2: VRC and DPR: the two reconfiguration schemes for EHW [3].…”

“…Systolic arrays are well suited for EHW systems and have been used several times [167,104,168,3,169,170]. A common paradigm for many systolic array implementations is to have functional cells in a rectangle shape with communication ports going in four directions (similar to type R).…”

“…HexArrays have many advantages over the traditional Cartesian systolic arrays (presented in [30] and other publications [173,3]), such as having a hybrid reconfiguration scheme, more inputs/outputs, higher parallelism, higher throughput, and can evolve to higher-order functions (i.e., has the potential to solve more complex problems …”

“…Typically, since systolic arrays are homogeneous systems, they do not allow this case. However, these applications are natively supported by HexArray 2 The AVRG function had a timing violation, resulting in 0x00 for most of the operations 3 In 1080p24 standard (1920x1080 pixels in 24 frame/sec) 166 using GLOBAL RULES. These are rules and constraints on cells' functions and output ports that all GAGA operators follow without violating.…”