Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis

Lin, Lang; Selvakumaran, Dinesh; Zhu, Deqi; Chang, Norman; Chow, Calvin; Nagata, Makoto; Monta, Kazuki

doi:10.1109/ises50453.2020.00038

Cited by 7 publications

(1 citation statement)

References 9 publications

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“…Recent work in the hardware security community has focused on developing tools and methodologies to capture and understand the impact of the physical sources of leakage at design time such that they can be mitigated before chip fabrication. For example, [116] proposes scalable approaches for evaluating the location-dependent side-channel leakage within the on-chip power distribution network (PDN). In addition, [152] finds that parasitics in the PDN break independence assumptions.…”

Section: Evaluation Of Probing Sensors and Physical Countermeasuresmentioning

confidence: 99%

Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

Covic,

Ganji,

Forte

2021

Preprint

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Side-channel attacks extracting sensitive data from implementations have been considered a major threat to the security of cryptographic schemes. This has elevated the need for improved designs by embodying countermeasures, with masking being the most prominent example. To formally verify the security of a masking scheme, numerous attack models have been developed to capture the physical properties of the information leakage as well as the capabilities of the adversary. With regard to these models, extensive research has been performed to realize masking schemes. These research efforts have led to significant progress in the development of security assessment methodologies and further initiated standardization activities. However, since the majority of this work is theoretical, it is challenging for the more practice-oriented hardware security community to fully grasp and contribute to. To bridge the gap, these advancements are reviewed and discussed in this survey, mainly from the perspective of hardware security. In doing so, a clear taxonomy is provided that is helpful for a systematic treatment of the masking-related topics. By giving an extensive overview of the existing methods, this survey (1) provides a research landscape of circuit masking for newcomers to the field, (2) offers guidelines on which attack model and verification tool to choose when designing masking schemes, and (3) identifies interesting new research directions where masking models and assessment tools can be applied. Thus, this survey serves as an essential reference for hardware security practitioners interested in the theory behind masking techniques, the tools useful to verify the security of masked circuits, and their potential applications.

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Section: Evaluation Of Probing Sensors and Physical Countermeasuresmentioning

confidence: 99%

Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

Covic,

Ganji,

Forte

2021

Preprint

View full text Add to dashboard Cite

show abstract

On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits

Monta,

Nagata,

Balasch

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification

Lin

Zhu

Wen

et al. 2021

2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Fast and Comprehensive Simulation Methodology for Layout-Based Power-Noise Side-Channel Leakage Analysis

Cited by 7 publications

References 9 publications

Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

On the Unpredictability of SPICE Simulations for Side-Channel Leakage Verification of Masked Cryptographic Circuits

Multiphysics Simulation of EM Side-Channels from Silicon Backside with ML-based Auto-POI Identification

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