Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA

Abstract

Modeling and simulation/emulation play a major role in research and development of novel Networks-on-Chip (NoCs). However, conventional software simulators are so slow that studying NoCs for emerging many-core systems with hundreds to thousands of cores is challenging. State-of-the-art FPGA-based NoC emulators have shown great potential in speeding up the NoC simulation, but they cannot emulate large-scale NoCs due to the FPGA capacity constraints. Moreover, emulating large-scale NoCs under synthetic workloads on FPGAs typically requires a large amount of memory and thus involves the use of off-chip memory, which makes the overall design much more complicated and may substantially degrade the emulation speed. This article presents methods for fast and cycle-accurate emulation of NoCs with up to thousands of nodes using a single FPGA. We first describe how to emulate a NoC under a synthetic workload using only FPGA on-chip memory (BRAMs). We next present a novel use of time-division multiplexing where BRAMs are effectively used for emulating a network using a small number of nodes, thereby overcoming the FPGA capacity constraints. We propose methods for emulating both direct and indirect networks, focusing on the commonly used meshes and fat-trees ( k -ary n -trees). This is different from prior work that considers only direct networks. Using the proposed methods, we build a NoC emulator, called FNoC, and demonstrate the emulation of some mesh-based and fat-tree-based NoCs with canonical router architectures. Our evaluation results show that (1) the size of the largest NoC that can be emulated depends on only the FPGA on-chip memory capacity; (2) a mesh-based NoC with 16,384 nodes (128×128 NoC) and a fat-tree-based NoC with 6,144 switch nodes and 4,096 terminal nodes (4-ary 6-tree NoC) can be emulated using a single Virtex-7 FPGA; and (3) when emulating these two NoCs, we achieve, respectively, 5,047× and 232× speedups over BookSim, one of the most widely used software-based NoC simulators, while maintaining the same level of accuracy.

LEF: An Effective Routing Algorithm for Two-Dimensional Meshes

“…To evaluate the performance of LEF compared to other routing algorithms, we use the FPGA-based NoC emulator proposed in [11] which is about two to three orders of magnitude faster than conventional software-based NoC simulators and can support designs with thousands of nodes. Another advantage of this FPGA-based NoC emulator is that it supports asymmetric networks which are not officially supported by some widely used software-based NoC simulators like BookSim [9].…”

“…Unfortunately, since these simulators are slow, most existing routing algorithms have not been evaluated in large-scale NoCs which consist of thousands of nodes. In this article, we use the fast and cycle-accurate FPGAbased NoC emulator proposed in [11] to evaluate LEF and its counterparts in networks of various sizes ranging from 8 × 8 to 128 × 64.…”

Accelerating Large-Scale Interconnection Network Simulation by Cellular Automata Concept

“…on a 64 × 64 system. Chu and Kise et al have proposed an extremely optimized operation on an FPGA platform to emulate NoCs [18], [19].…”

3D NoC emulation model on a single FPGA

“…Before the actual implementation of the NoC, it needs to be thoroughly evaluated to fine-tune the design choices. Therefore, NoC modeling and simulation/emulation play a critical role in designing novel MPSoCs, particularly those with hundreds to thousands of cores [5].…”

“…Although they can deliver very accurate results while being flexible, the simulation time is likely to be prohibitive for large designs. For instance, it would take almost a year for gem5 to simulate a thousand-core chip [5,19].…”