Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

Mizuno, Kosuke; Noguchi, Hiroki; He, Guangji; Terachi, Yosuke; Kamino, Tetsuya; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.1109/fpl.2010.119

Cited by 30 publications

(16 citation statements)

References 4 publications

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“…Also, since most interest point detectors rely on the generation of the Gaussian pyramid and the application of a differentiation operator to the generated scales, only SIFT realizations are covered; the conclusions drawn for SIFT apply to other algorithms. Out from the SIFT implementations addressed here, [43] - [45] correspond to FPGA implementations, while [46] and [47] correspond to custom chips. None of these implementations includes the sensing devices; in all cases images are provided by separate, external sensors.…”

Section: B Overview Of Feature Detectors Hardware Artmentioning

confidence: 99%

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CMOS-3D Smart Imager Architectures for Feature Detection

Suarez

Brea

Fernández-Berni

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3D IC technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixedsignal domain. It embeds in-pixel Correlated Double Sampling (CDS), a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel ADC (Analog to Digital Conversion). This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian and DoG detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a Switched-Capacitor (SC) network in less than 50 µs, outperforming more conventional solutions.

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Section: B Overview Of Feature Detectors Hardware Artmentioning

confidence: 99%

“…In [43] the image is split into regions of interest and a pipeline flow is realized at each region, thus increasing parallelism. Frame rates of 56fps for VGA images are obtained by using a pyramid with 18 modules (3 octaves with 6 scales each).…”

Section: B Overview Of Feature Detectors Hardware Artmentioning

confidence: 99%

CMOS-3D Smart Imager Architectures for Feature Detection

Suarez

Brea

Fernández-Berni

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…Two CMOS implementations are described in [21,22], which reach the same frame rate for VGA and HD1080 images respectively. Finally, in [23][24][25], three pure hardware FPGA implementations able to generate descriptors at a faster rate (above 50 fps) are described. However, these fast implementations require some simplifications to the original algorithm in order to achieve such processing rates.…”

Section: Introductionmentioning

confidence: 99%

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

Doménech‐Asensi

Ruiz‐Merino

Zapata

et al. 2017

2017 32nd Conference on Design of Circuits and Integrated Systems (DCIS)

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Abstract-This paper describes a hardware proposal to speed up the process of image matching in stereo vision systems like those employed by autonomous mobile robots. This proposal combines a classical window-based matching approach with a previous stage, where key points are selected from each image of the stereo pair. In this first step the key point extraction method is based on the SIFT algorithm. Thus, in the second step, the window-based matching is only applied to the set of selected key points, instead of to the whole images. For images with a 1% of key points, this method speeds up the matching four orders of magnitude. This proposal is, on the one hand, a better parallelizable architecture than the original SIFT, and on the other, a faster technique than a full image windows matching approach. The architecture has been implemented on a lower power Virtex 6 FPGA and it achieves a image matching speed above 30 fps.

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“…The value of V also differs in [3]. Some IP kernels are introduced to calculate the filtering such as MAC and MUX in [2]. The second step is the Detection of Key Points.…”

Section: Introductionmentioning

confidence: 99%

“…The first step is the Generation of Gaussian Pyramid. ROI is introduced to generate suitable initial images in [2] and initial images are divided into smaller partitions in [3]. The size of Gaussian window function varies in [3]- [6], even the number of scales and octaves [7].…”

Section: Introductionmentioning

confidence: 99%

An Optimized Structure on FPGA of Key Point Detection in SIFT Algorithm

Zhu

et al. 2016

MATEC Web of Conferences

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Abstract. SIFT algorithm is the most efficient and powerful algorithm to describe the features of images and it has been applied in many fields. In this paper, we propose an optimized method to realize the hardware implementation of the SIFT algorithm. We mainly discuss the structure of Data Generation here. A pipeline architecture is introduced to accelerate this optimized system. Parameters' setting and approximation's controlling in different image qualities and hardware resources are the focus of this paper. The results of experiments fully prove that this structure is real-time and effective, and provide consultative opinion to meet the different situations.

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Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video

Cited by 30 publications

References 4 publications

CMOS-3D Smart Imager Architectures for Feature Detection

CMOS-3D Smart Imager Architectures for Feature Detection

FPGA synthesis of an stereo image matching architecture for autonomous mobile robots

An Optimized Structure on FPGA of Key Point Detection in SIFT Algorithm

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