FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

Hellebrand, Sybille; Indlekofer, Thomas; Kampmann, Matthias; Kochte, Michael A.; Liu, Chang; Wunderlich, Hans-Joachim

doi:10.1109/test.2014.7035360

Cited by 34 publications

(5 citation statements)

References 29 publications

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“…• Tools such as timing-aware simulation tool [54] as well as Static Timing Analysis (STA) [55] can randomly select from the already generated cell characterization library and use them for timing analysis and generating the required vectors M c . • During the chip manufacturing, vectors M c can be obtained directly from real measurements at the speedbinning [32] or faster-than-at-speed test [4].…”

Section: Application Scenariosmentioning

confidence: 99%

“…Resistive opens and resistive bridges result often in SDFs [1,2,3] which are hard to detect during production testing. Since they may evolve rather early in the circuits lifetime and turn into catastrophic faults, they have to be covered during the test of high-quality systems [4,5,6]. It is well known that testing at varying voltages and especially low voltage testing increase the fault coverage significantly [7,8,9,10], and modern systems with Adaptive Voltage Frequency Scaling (AVFS) have all the means to support this test strategy [11].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Identifying Resistive Open Defects in Embedded Cells under Variations

Najafi-Haghi

Wunderlich

2023

J Electron Test

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Small Delay Faults (SDFs) due to weak defects and marginalities have to be distinguished from extra delays due to process variations, since they may form a reliability threat even if the resulting timing is within the specification. In this paper, it is shown that these faults can still be identified, even if the corresponding defect cell is deeply embedded into a combinational circuit and its observability is restricted. The results of a few delay tests at different voltages and frequencies serve as the input to machine learning procedures which can classify a circuit as marginal due to defects or just slow due to variations. Several machine learning techniques are investigated and compared with respect to accuracy, precision, and recall for different circuit sizes and defect scales. The classification strategies are powerful enough to sort out defective devices without a major impact on yield.

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Section: Application Scenariosmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Identifying Resistive Open Defects in Embedded Cells under Variations

Najafi-Haghi

Wunderlich

2023

J Electron Test

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“…Using properly selected frequencies, FAST can be e±ciently implemented as Built-In Self-Test (BIST) as shown in Ref. 9. However, overclocking the circuit during FAST also introduces new challenges, especially for BIST and embedded test.…”

Section: Introductionmentioning

confidence: 99%

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

Sprenger

Hellebrand

2019

J CIRCUIT SYST COMP

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With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([Formula: see text]-values). These [Formula: see text]-values impede the test response compaction. In addition, the number and distribution of the [Formula: see text]-values vary with the clock frequency, and thus a very flexible [Formula: see text]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [Formula: see text]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [Formula: see text]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [Formula: see text]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [Formula: see text]-reduction and fault efficiency can be adapted to user-defined goals.

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“…Regarding new stress techniques, recent studies are beginning to consider the execution of patterns with a clock frequency higher than the nominal at-speed. This technique, known as faster-than-at-speed test (FAST), finds satisfying results when applied for detecting small delay defects (SDD) which are not easy to screen out with at-speed test [4], [5].…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, built-in FAST using programmable on-chip clock generation is comfortable with these issues [6][7], as frequency increase is functionally obtained (e.g., executing assembly instructions). Current works concentrate their efforts on classifying faults according to the optimal frequency they can be tested, or on finding an optimized selection of clock frequencies [4], [8]; usually the maximum clock rate value may be up to 3 times higher than the nominal clock rate [4], [9][10].…”

Section: Introductionmentioning

confidence: 99%

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs

Bernardi

Bosio

Natale

et al. 2017

IFIP Advances in Information and Communication Technology

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At the end of the manufacturing cycle of digital circuits, a stress phase is mandatory in order to remove from the final device population the weak devices that may result in early life failures. Devices used in safety critical environments must undergo this phase that is usually accomplished by exploiting the Burn-In (BI) process. Unfortunately, BI has elevated costs for companies and current state of the art techniques are trying to reduce its cost. In recent days, Faster-than-at-Speed-Test (FAST) has become a useful technique to discover small delay defects. At the same time, overclocking methods to enhance system performances have been studied, which focus on temperature management to preserve system functionalities. In this contribution, a FAST technique is proposed with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of FAST functional test programs; in other words, functional procedures are executed at higher than nominal frequencies. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults. Being the functional stress procedures executed at faster than nominal speed, the original behaviour may not be preserved and therefore non-functional states may be reached. In this contribution, it is illustrated how to avoid blocking configurations due to timing constraints violation and how to obtain a significant increase of the switching activity by carefully increasing the clock frequency. Furthermore, a novel strategy is proposed to generate a suitable set of Faster-than-At-Speed stress programs capable to thoroughly stress processor cores. Experimental results carried out on a MIPS-like architecture show major achievements of the methodology: the processor may work at frequencies up to about 20 times higher than the nominal one without falling into an unpredictable state and the switching activity is increasing up to 300% per nanoseconds.

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FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects

Cited by 34 publications

References 29 publications

Identifying Resistive Open Defects in Embedded Cells under Variations

Identifying Resistive Open Defects in Embedded Cells under Variations

Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs

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