2017 14th IEEE India Council International Conference (INDICON) 2017
DOI: 10.1109/indicon.2017.8487598
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Fast Combinational Architecture for a Vedic Divider

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Cited by 7 publications
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“…These iterative algorithms are implemented sequentially and have a long latency, a significant area overhead and consume a large amount of power compared to the other mathematical operations [34]. Therefore, many reduction approaches can reduce the number of division cycles, thus reducing power dissipation [35].…”
Section: Division Algorithmmentioning
confidence: 99%
“…These iterative algorithms are implemented sequentially and have a long latency, a significant area overhead and consume a large amount of power compared to the other mathematical operations [34]. Therefore, many reduction approaches can reduce the number of division cycles, thus reducing power dissipation [35].…”
Section: Division Algorithmmentioning
confidence: 99%