Abstract. This paper presents a more complex algorithm with Verilog-HDL, which based on the dual-modulus preseted decimal frequency divider. This algorithm can not only increase the accuracy of decimal frequency divider. , but also can be used to divide a clock. Simulations are conducted to analyze the characteristics of the decimal frequency divider and DDS divider. The results shows that the divider can satisfy the requirements of design.
I. INTRODUTIONIn the 21st century the development of digital integrated circuits become more and more important in the design field of IC. Compared with the analog circuits, digital circuits show great advantages in power consumption. And algorithm of digital circuits is easy to implement. Therefore, the study of digital circuits becomes very significant [1].As we all know, the digital systems can work normally according to a beat. The beat is the signal of clock which is generated by a clock circuit. The clock circuit is composed of crystal oscillator. The crystal oscillator can provide a stable clock. However, this clock is always different from the required clock which is based on the frequency of input clock. It's necessary to design a frequency divider to divide the input clock into different frequencies and assign the divided clock to the other modules. To sum up, the design of the frequency synthesizer becomes the most basic and most critical part of the digital IC design.The divider is a very important basis part of the digital IC design [2][3]. And the integer frequency divider is easy to achieve. But in most instances, the frequency division ratio is not an integer number. In this case we need a fractional divider to divide the input clock. Now the fractional divider can be implemented mainly by the following ways: 1）the Phase-locked Loop frequency synthesizer. 2）Direct Digital Synthesizer. Both frequency synthesis modes can get a precision performance. However, both frequency synthesis methods would consume a lot of circuit resources. Therefore in some circumstances, such as the circuit's resources are scarce relatively, the circuit needs a low-power clock. In such cases, the digital programming fractional divider can be used.Because of the above idea, this paper proposes a high-precision fractional divider that based on Verilog-HDL, which can reach a reliable division results. And at the end of the paper a comparison between the fractional divider and DDS is presented.
II. THE ALGORITHM OF HIGH-ACCURACY DECIMAL FREQUENCY DIVIDER
A. Design PrinciplesThe core idea of this design lies in the dual-modulus decimal frequency division, which means to overcount or undercount a pulse to get the decimal frequency value on average [4]. Provided that K is the decimal value of crystal frequency-output frequency ratio, K can be expressed as:(1) Where N represents the integral part of K, andA/B represents the decimal part of K.A is less than B. When frequency coefficient K is a n-bits decimal number, B equals 10n. If N+1 decimal frequency is just conducted for B times and then N...
