20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07) 2007
DOI: 10.1109/vlsid.2007.82
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Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits

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“…Lingappan et al also enhance the ADD based test generation technique by control-data flow graphs (CDFG) and state transition sequence analysis in [21,22]. Further on, the technique is enhanced by Boolean implications (also known as as the unsatisfiable segment) in [23,24].…”
Section: Control And/or Datapath Oriented Rtl Fault Modelsmentioning
confidence: 99%
“…Lingappan et al also enhance the ADD based test generation technique by control-data flow graphs (CDFG) and state transition sequence analysis in [21,22]. Further on, the technique is enhanced by Boolean implications (also known as as the unsatisfiable segment) in [23,24].…”
Section: Control And/or Datapath Oriented Rtl Fault Modelsmentioning
confidence: 99%