Fast exact toffoli network synthesis of reversible logic

Abstract

Abstract-The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude. I. INTRODUCTIONReversible logic has applications in low-power design, optical computing and especially in quantum computing. In the context of quantum computation it is known that some exponentially hard problems can be solved in polynomial time [1]. Necessarily all quantum computations are reversible. Therefore synthesis of reversible logic has become an intensively studied topic. The synthesis of reversible logic differs significantly from traditional irreversible logic. In a reversible network fan-out and feed-back are not allowed. Consequently a network for reversible logic consists of a cascade of reversible gates. The most frequently used gate type is the Toffoli gate [2] which will also be used in this paper. The idea of this gate is to invert one input line (the target line) if the product of a set of control lines evaluates to true.For the synthesis of reversible logic several approaches have been proposed. An approach that is based on enumeration and that uses network equivalences to rewrite a limited set of gates has been presented in [3]. Other synthesis procedures use heuristics like e.g. spectral techniques [4], positive polarity Reed-Muller expansions [5] or transformation based synthesis [6]. In [7] a method has been proposed that synthesizes the reversible function in a first step and then based on transformations (using so called templates) a realization with fewer gates is computed. An exact synthesis method based on reachability analysis is described in [8]. However, this procedure is geared towards quantum gates, not Toffoli gates. Recently, in [9] the first exact synthesis approach for reversible logic using generalized Toffoli gates has been presented. This approach uses Boolean Satisfiability (SAT) during the synthesis process. Since the synthesis problem is transformed to the Boolean level complexity problems occur.The contribution of this paper is twofold. First, we lift the encoding of the synthesis problem to a higher level. Based on this formulation, the SAT solver used in [9] is replaced by a Satisfiability Modulo Theories (SMT) solver. As shown by the experiments this already leads to a significant speed-up of the synthesis algorithm. Second, after a detailed analysis of the principle limits of these synthesis procedures we propose a compl...

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“…As the main objective the number of gates is minimized as done by many other researchers (see e.g. [5,9,11,15,16,20]). The proposed methodology can also be adapted for other gate libraries as well as other objectives.…”