Fast factorization architecture in soft-decision Reed-Solomon decoding

IEICE Electron. Express

Liu

Zheng

et al. 2023

This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA is proposed with a fully-parallel architecture. An optimized adaptive error correction approach is utilized to reduce the power consumption. Furthermore, the composite field arithmetic is used to minimize the logical size. For the performance evaluation, the decoder is implemented on a Xilinx Virtex-7 FPGA, and synthesized with 65nm CMOS technology, which can achieve a 62.72 Gb/s throughput at a decoding frequency of 490MHz and 0.95ns decoding delay with a 774.1 μW power consumption.

Section: Reducing Logic Complexity With Composite Field Arithmeticmentioning

confidence: 99%

High-speed and low-power embedded TEC BCH scheme for ReRAM array

IEICE Electron. Express

Liu

Zheng

et al. 2023

“…The main benefit of LCC is the use of just one level of multiplicity, which means that only the relationship between the hard-decision (HD) reliability value of the received symbols and the second best decision is required to exploit the soft-information from the channel. This fact has a great impact on the number of iterations and on the global complexity of the interpolation and factorization steps [10][11][12][13][14][15][16] compared to KV and BGMD [17]. Another benefit derived from having just one level of multiplicity is that the interpolation and factorization stages can be replaced by Berlekamp-Massey decoders [18], and this results in a considerable reduction in the total number of operations [19].…”

Section: Introductionmentioning

confidence: 99%

Soft-Decision Low-Complexity Chase Decoders for the RS(255,239) Code

et al. 2018

In this work, we present a new architecture for soft-decision Reed–Solomon (RS) Low-Complexity Chase (LCC) decoding. The proposed architecture is scalable and can be used for a high number of test vectors. We propose a novel Multiplicity Assignment stage that sorts and stores only the location of the errors inside the symbols and the powers of α that identify the positions of the symbols in the frame. Novel schematics for the Syndrome Update and Symbol Modification blocks that are adapted to the proposed sorting stage are also presented. We also propose novel solutions for the problems that arise when a high number of test vectors is processed. We implemented three decoders: a η = 4 LCC decoder and two decoders that only decode 31 and 60 test vectors of true η = 5 and η = 6 LCC decoders, respectively. For example, our η = 4 decoder requires 29% less look-up tables in Virtex-V Field Programmable Gate Array (FPGA) devices than the best soft-decision RS decoder published to date, while has a 0.07 dB coding gain over that decoder.

Modified Low-Complexity Chase Soft-Decision Decoder of Reed–Solomon Codes

Zhu

2010

J Sign Process Syst

Reed-Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can achieve substantial coding gain with polynomial complexity. Among practical ASD algorithms, the low-complexity chase (LCC) algorithm that tests 2 η vectors can achieve similar or higher coding gain with lower complexity. For applications such as magnetic recording, the performance of the LCC decoding is degraded by the inter-symbol interference from the channel. Improving the performance of the LCC decoding requires larger η, which leads to higher complexity. In this paper, a modified LCC (MLCC) decoding is proposed by adding erasures to the test vectors. With the same η, the proposed algorithm can achieve much better performance than the original LCC decoding. One major step of the LCC and MLCC decoding is the interpolation. To reduce the complexity of the interpolation, this paper also proposed a prioritized interpolation scheme to test a small proportion of the vectors at a time, starting with the ones with higher reliabilities. For a (458, 410) RS code, by testing 1/8 of the vectors at a time, the area requirement of the MLCC decoder with η = 8 can be reduced to 57%, and the average decoding latency is reduced to 73%.