Fast FFT-Based Inference in 3D Convolutional Neural Networks

Xie, Bo; Zhang, Guidong; Shen, Yongjun; Liu, Shun; Ge, Yabin

doi:10.1007/978-3-319-93554-6_40

Cited by 1 publication

(1 citation statement)

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“…To theoretically boost the computational rate of convolutional neural network (CNN) accelerators, Lee et al [7] developed a novel method called double MAC, which doubles the computational throughput of CNN layers by packaging two MAC operations into a single digital signal processing (DSP) block. Furthermore, Xie et al [8] optimized network throughput, energy consumption, and execution time by simplifying matrix multiplication using Fast Fourier Transform (FFT) in convolution, thereby reducing the complexity of convolution layers. Kang et al [9] proposed a mixed-precision MAC unit structure that supports both low-precision and high-precision multiplication modes, reducing the cost of multiplication operations and energy consumption compared to traditional MAC structures.…”

Section: Related Workmentioning

confidence: 99%

Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies

et al. 2023

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Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications.

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Section: Related Workmentioning

confidence: 99%