Fast Linking of Separately-Compiled FPGA Blocks without a NoC

Xiao, Yuanlong; Ahmed, Syed Tousif; DeHon, André

doi:10.1109/icfpt51103.2020.00035

Cited by 11 publications

(2 citation statements)

References 33 publications

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“…Wider network interfaces and networks with less link sharing will support higher performance at the expense of larger overhead. By cutting the network region up into switch pages, it would be possible to dedicate unshared wire connections between operators and separately compile the application-customized linking switch pages, as well [64].…”

Section: Linking Networkmentioning

confidence: 99%

“…This can consume a large number of BRAMs along with LUTs to support those BRAMs and their synchronization. One promising solution is to use Relay Station [64] to connect operators together, instead of stream FIFOs. However, this requires care to set the buffer sizes appropriately to avoid introducing deadlock that was not part of the original design.…”

Section: Area Evaluationmentioning

confidence: 99%

See 1 more Smart Citation

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development

Xiao

Micallef

Butt

et al. 2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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FPGA-based accelerators are demonstrating significant absolute performance and energy efficiency compared with general-purpose CPUs. While FPGA computations can now be described in standard, programming languages, like C, development for FPGAs accelerators remains tedious and inaccessible to modern software engineers. Slow compiles (potentially taking tens of hours) inhibit the rapid, incremental refinement of designs that is the hallmark of modern software engineering. To address this issue, we introduce separate compilation and linkage into the FPGA design flow, providing faster design turns more familiar to software development. To realize this flow, we provide abstractions, compiler options, and compiler flow that allow the same C source code to be compiled to processor cores in seconds and to FPGA regions in minutes, providing the missing -O0 and -O1 options familiar in software development. This raises the FPGA programming level and standardizes the programming experience, bringing FPGA-based accelerators into a more familiar software platform ecosystem for software engineers. CCS CONCEPTS• Hardware → Reconfigurable logic and FPGAs; • Software and its engineering → Development frameworks and environments.

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Section: Linking Networkmentioning

confidence: 99%

Section: Area Evaluationmentioning

confidence: 99%