Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Kakacak, Ahmet; Guzel, Aydin Emre; Cihangir, Ozan; Gren, Sezer; Uğurdağ, H. Fatih

doi:10.1016/j.vlsi.2016.12.012

Cited by 19 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As an example, Woo et al [44] implements three different multiplication algorithms on FPGAs and these algorithms can multiply two 8-bit numbers with a latency of 5 cycles. Similarly, Kakacak et al [26] claim to achieve better timings than the state of the art in the literature, yet their implementations require 7ns to multiply two 64-bits numbers. A recent architecture like AMD Zen 2 using GMP requires around 1.75 clock cycles per 64-bits when multiplying numbers.…”

Section: Faster Hardwarementioning

confidence: 99%

Delay Encryption by Cubing

Maffei¹,

Roscoe²

2022

Preprint

View full text Add to dashboard Cite

Delay Encryption (often called Timed-Release Encryption) is a scheme in which a message is sent into the future by ensuring its confidentiality only for a given amount of time. We propose a new scheme based on a novel time-lock puzzle. This puzzle relies on the assumption that repeated squaring is an inherently sequential process. We perform an extensive and practical analysis of many classical and quantum attacks on our scheme and conclude that it is secure given some precautions.

show abstract

Section: Faster Hardwarementioning

confidence: 99%

Delay Encryption by Cubing

Maffei¹,

Roscoe²

2022

Preprint

View full text Add to dashboard Cite

show abstract

“…In [4], a viable technique is proposed for changing over a double number into a RNS dependent on isolating the first multi-bit parallel number into independent parts, for which a foreordained number of paired digits B are designated. At that point a n-cycle twofold number can be communicated as a mix of weighted (positional) numbers with the measurement B (bits) [5][6][7]. For this situation, the places of every such part are allocated a specific weight 2j, where j = 0, B, 2B, ..., MB.…”

Section: Introductionmentioning

confidence: 99%

Study of effective calculation operation implementation remaining multi-bit numbers division on FPGA

Al-Hilali¹,

Jumaa²,

Amory³

2022

PEN

View full text Add to dashboard Cite

The rapid enhancement in the fields of the computers that leads to rapid breaking for ciphering algorithms and for these reasons most of ciphering algorithm tried to used multidigit for ciphering texts or images. Using multidigit will increase the safety of information and protected it from supercomputer from breaking the ciphering algorithms. The current information systems employ operations on finite fields of various structures (for example, cryptographic systems). In this instance, it's common to have to deal with enormous numbers (128 bits or more). The proposed operation of discovering the remainder of the division of multidigit numbers will considerably improve the speed of such systems if implemented.

show abstract

“…The existing multipliers are high-speed Baugh Wooley [6], Baugh Wooley with unsigned [7], approximate multiplier with carry predictor [8], energy-efficient approximate multiplier [9], modified retiming serial multiplier [10], fast multiplier [11], Montgomery multiplier [12], array multiplier [13], etc. These multipliers require more power and area for performing the multiplication.…”

Section: Introductionmentioning

confidence: 99%

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Monica¹,

Anuradha²,

Syed³

et al. 2021

IJIES

View full text Add to dashboard Cite

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

show abstract

Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Cited by 19 publications

References 12 publications

Delay Encryption by Cubing

Delay Encryption by Cubing

Study of effective calculation operation implementation remaining multi-bit numbers division on FPGA

VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

Contact Info

Product

Resources

About