FAST-Net optical interconnection prototype demonstration

Haney, Michael W.; Christensen, Marc P.; Milojkovic, Predrag; Ekman, J.; Chandramani, P.; Rozier, R. Gary; Kiamilev, Fouad; Liu, Yue; Hibbs‐Brenner, Mary K.; Nohava, J.C.; Kalweit, E.; Bounnak, Sommy; Marta, Terry; Walterson, B.

doi:10.1117/12.308879

Cited by 13 publications

(9 citation statements)

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“…As part of the FAST-Net ͑Free-Space Accelerator for Switching Terabit Networks͒ prototype program, efforts are now focused on the implementation of the two-bounce architecture with MCM's of smart pixels consisting of high-density VCSEL͞detector arrays integrated with high-performance complementary metal-oxide semiconductor logic. 25 Aspects of this study have been sponsored by the U.S. Defense Advanced Research Projects Agency and the Ballistic Missile Defense Organization through contracts monitored by the U.S. Air Force Office of Scientific Research.…”

Section: Discussionmentioning

confidence: 99%

Two-bounce optical arbitrary permutation network

Christensen

Haney

1998

Appl. Opt.

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The two-bounce free-space arbitrary interconnection architecture is presented. It results from a series of three-dimensional topological transformations to the Benes network, the minimum rearrangeable nonblocking network. Although functionally equivalent to the Benes network, it requires only two stages of global (spanning multiple chips) optical interconnections. The remaining stages of the modified Benes interconnection network are local and are implemented electronically (on individual chips). The two-bounce network is optimal in the sense that it retains the Benes minimum number of electronic switching resources yet also minimizes the number of optical links needed for global interconnection. Despite the use of higher-order k-shuffle (k > 2) global optical interconnects, the number of 2 x 2 switching elements is identical to the two-shuffle Benes network: there is no need for k x k crossbar switches for local interconnection at each stage. An experimental validation of the two-bounce architecture is presented.

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Section: Discussionmentioning

confidence: 99%

Two-bounce optical arbitrary permutation network

Christensen

Haney

1998

Appl. Opt.

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“…This scale is the self-similar replication of one chip in the array (Fig. 11) reduced to represent one cluster on the chip [38].…”

Section: Fractal Configurationsmentioning

confidence: 99%

Review of multiscale optical design

Milojkovic

Christensen

2015

Appl. Opt.

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Multiscale optical design is an approach that has been successfully utilized for over 100 years by optical designers and engineers to overcome challenges and achieve desired optical system performance. The benefits of the design paradigm include improving light collection, creating specific symmetries that can be exploited, collecting additional information about the object space, partitioning the optical field to enable piecewise correction of aberrations, and alleviating packing constraints. The purpose of this paper is to review the historical emergence of the use of multiscale optical design and present key examples of developments that have expanded its capabilities over the years.

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“…In a real application, the silicon CMOS ASIC attached to the optoelectronic chip could be a microprocessor, or a digital signal processor, or router chip that needs to be connected to another chip in a MCM. Under the government funded research program called "VLSI Photonics," the R&D group of Honeywell VCSEL Optical Products participated in several projects [4], [5], [7] that explored varieties of architectural configuration designed to enhance information processing systems performance by increase interconnectivity capacity using massively parallel free-space optical interconnect.…”

Section: Fabrication and Integrationmentioning

confidence: 99%

Heterogeneous integration of OE arrays with Si electronics and microoptics

Liu

2002

IEEE Trans. Adv. Packag.

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This paper describes recent developments of the smart pixel array (SPA) technology for massively parallel optical interconnect applications. Built on Honeywell's commercially successful 850 nm vertical cavity surface emitting lasers (VC-SELs) technology, the SPA employs two-dimensional (2-D) array of VCSELs and Photodetectors (PDs). It aims to push optical interconnect density and capacity to a new level, which brings chip-level input and output (IO) capacity to the order of 100s to 1000s of gigabit per second (Gbps). This technology has following unique features that make it not only technically feasible but also practical for low cost manufacturing. First, it employs optoelectronic (OE) array based on the new generation of oxide-confined VCSELs that have desired characteristics such as very high speed, high efficiency, and good array uniformity. Second, the OE array has monolithically integrated VCSELs and PDs that provides true bi-directional optical I/O solutions at the chip-scale. Third, it uses hybrid integration techniques such as solder bump bonding and wafer scale integration. The 2-D arrays of VCSELs and PDs can be seamlessly integrated with beam shaping micro-optics array, and with the state-of-the-art Si-based VLSI electronic ICs. Last, and perhaps most importantly, all of the technology implementations follow the guideline of being compatible with mainstream low cost manufacturing practices.Device performance characteristics, integration approach, and prototype demonstration SPA technology up to over 1000 IO channels per chip will be presented, including some early system prototype demonstrations. We believe the SPA technology provides future application specific integrated circuits (ASICs) with new form packaging solutions-a solution that give an ASIC with unprecedented large capacity of very high density and high speed I/Os. It can be used as a new building block to implement varieties of system architectures that are not possible to build with today's electrical interconnection.

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FAST-Net optical interconnection prototype demonstration

Cited by 13 publications

References 0 publications

Two-bounce optical arbitrary permutation network

Two-bounce optical arbitrary permutation network

Review of multiscale optical design

Heterogeneous integration of OE arrays with Si electronics and microoptics

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