Fast on-chip inductance simulation using a precorrected-FFT method

Abstract

In this paper, a precorrected-fast-Fourier-transform (FFT) approach for fast and highly accurate simulation of circuits with on-chip inductance is proposed. This work is motivated by the fact that circuit analysis and optimization methods based on the partial element equivalent circuit model require the solution of a subproblem in which a dense inductance matrix must be multiplied by a given vector, an operation with a high computational cost. Unlike traditional inductance extraction approaches, the precorrected-FFT method does not attempt to compute the inductance matrix explicitly, but assumes the entries in the given vector to be the fictitious currents in inductors and enables the accurate and quick computation of this matrix-vector product by exploiting the properties of the inductance calculation procedure. The effects of all of the inductors are implicitly considered in the calculation: faraway inductor effects are captured by representing the conductor currents as point currents on a grid, while nearby inductive interactions are modeled through direct calculation. The grid representation enables the use of the discrete FFT for fast magnetic vector potential calculation. The precorrected-FFT method has been applied to accurately simulate large industrial circuits with up to 121 000 inductors and over 7 billion mutual inductive couplings in about 20 min. Techniques for trading off CPU time with accuracy using different approximation orders and grid constructions are also illustrated. Comparisons with a block-diagonal sparsification method are used to illustrate the accuracy and effectiveness of this method. In terms of accuracy, memory, and speed, it is shown that the precorrected-FFT method is an excellent approach for simulating on-chip inductance in a large circuit.

Fast Galerkin BEM for 3D-potential theory

“…If q = 3, then the near-neighboring region of a non-empty cell is formed not only with the considered cell itself but also with all non-empty cells that have a common vertex with the designated cell. This situation is sometimes referred to as the first nearest neighbors [8]. With these definitions, q simply defines the near-neighboring region in the precorrection process of the PFFT algorithm and affects the memory and accuracy of the PFFT method via the conventional near-field calculation.…”

“…Following the standard approach for solving (8), the double integrations in (9) are explicitly evaluated. In doing so, appropriate techniques are used to treat singular integrals [6].…”

Consideration of parasitic effects on buses during early IC design stages

“…In order to get a PEEC model we used a precorrected-fast-Fourier-transform (FFT) approach [8] to chip inductance. The merits of this method are that the dense inductance matrix is not calculated exp accurate and fast computation of the product of the inductance matrix with a given vector is provided.…”

“…But our approach is to use model order reduction which is considered [2] for the fully-dense matrix of their model. tance Extraction et a PEEC model we used a precorrected-fast-Fourier-transform (FFT) approach [8] to simulate the once. The merits of this method are that the dense inductance matrix is not calculated explicitly, but a very fast computation of the product of the inductance matrix with a given vector is provided.…”

“…The merits of this method are that the dense inductance matrix is not calculated explicitly, but a very fast computation of the product of the inductance matrix with a given vector is provided. Further this method r the problems of other sparsification techniques which are also described in detail in [8]. It considers all l inductances and is based on accurate partial inductance formulas.…”