Fast pipelined storage for high-performance energy-efficient computing with superconductor technology

Dorojevets, Mikhail; Chen, Zuoting

doi:10.1109/cewit.2015.7338159

Cited by 9 publications

(7 citation statements)

References 15 publications

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“…s st em = at e + int er connect (1) Table 5 shows the JJ-complexity of some commonly used logic blocks. For validation, we compare our method of evaluating JJcomplexity against published designs that use foundry RQL standard cell library based on foundry models and observe that our estimates are within 12% of the numbers reported in prior work [4,16].…”

Section: Modeling Area Using Jj-complexitymentioning

confidence: 78%

“…Other demonstrated circuits include shift registers, small arithmetic circuits, transmission driver systems, and serial data receiver systems [12][13][14][15]. Design and resource estimates exist for 32-bit and 64-bit integer and floating-point arithmetic and logical units, register file, on-chip storage components, bloom filters [4,16,17]. Table 1 compares the energy-efficiency of typical operations in 16-nm CMOS and superconducting technology.…”

Section: C) Circuit Schematicmentioning

confidence: 99%

“…As JJ-based logic gates have limited driving strength, JTLs are inserted to facilitate the desired fanout. In this paper, we use JJ-complexity as a key figure of merit, similar to prior superconducting system designs [4,16]. We evaluate the system level JJ-complexity by computing gate JJcomplexity and interconnect JJ-complexity.…”

Section: Modeling Area Using Jj-complexitymentioning

confidence: 99%

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A case for superconducting accelerators

Tannu

Das

Lewis

et al. 2019

Proceedings of the 16th ACM International Conference on Computing Frontiers

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As the scaling of conventional CMOS-based technologies slows down, there is growing interest in alternative technologies that can improve performance or energy-efficiency. Superconducting circuits based on Josephson Junction (JJ) is an emerging technology that can provide devices which can be switched with pico-second latencies and consuming two orders of magnitude lower switching energy compared to CMOS. While JJ-based circuits can provide high operating frequency and energy-efficiency, this technology faces three critical challenges: limited device density and lack of area-efficient technology for memory structures, reduced gate fanout compared to CMOS, and new failure modes of Flux-Traps that occurs due to the operating environment.The lack of dense memory technology restricts the use of superconducting technology in the near term to application domains that have high compute intensity but require negligible amount of memory. In this paper, we study the use of superconducting technology to build an accelerator for SHA-256 engines commonly used in Bitcoin mining applications. We show that merely porting existing CMOS-based accelerator to superconducting technology provides 10.6X improvement in energy efficiency. Redesigning the accelerator to suit the unique constraints of superconducting technology (such as low fanout) improves the energy efficiency to 12.2X. We also investigate solutions to make the accelerator tolerant of new fault modes and show how this fault-tolerant design can be leveraged to reduce the operating current, thereby increasing the overall energy-efficiency to 46X compared to CMOS. Our paper also develops a workflow for evaluating area, performance, and power for accelerators built in superconducting technology, and this workflow can help other researchers explore designs using this technology.

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Section: Modeling Area Using Jj-complexitymentioning

confidence: 78%

Section: C) Circuit Schematicmentioning

confidence: 99%

Section: Modeling Area Using Jj-complexitymentioning

confidence: 99%

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A case for superconducting accelerators

Tannu

Das

Lewis

et al. 2019

Proceedings of the 16th ACM International Conference on Computing Frontiers

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“…Several types of the local storage component, such as register file and small-capacity memory, have been demonstrated [6]- [10] or designed [11]. Shift-register-based storage [12] is considered to be the most convenient option for RSFQ bit-serial microprocessors because it is dc biased, capable of operating at a clock frequency exceeding several tens of gigahertz, and composed of serially connected D flip-flops that are very suitable for implementation with RSFQ circuits, whereas much higher bandwidth is achieved by using bitparallel processing [10], [11].…”

Section: Introductionmentioning

confidence: 99%

“…Shift-register-based storage [12] is considered to be the most convenient option for RSFQ bit-serial microprocessors because it is dc biased, capable of operating at a clock frequency exceeding several tens of gigahertz, and composed of serially connected D flip-flops that are very suitable for implementation with RSFQ circuits, whereas much higher bandwidth is achieved by using bitparallel processing [10], [11]. An ultimately efficient implementation of the shift register was demonstrated, in which only two Josephson junctions were used to realize each bit [13].…”

Section: Introductionmentioning

confidence: 99%

High-Density Shift-Register-Based Rapid Single-Flux-Quantum Memory System for Bit-Serial Microprocessors

Tanaka

Sato

Hatanaka

2016

IEEE Trans. Appl. Supercond.

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We demonstrated a high-density shift-register-based random access memory system based on rapid single-fluxquantum (RSFQ) logic. This memory system was developed to be integrated with bit-serial RSFQ microprocessors, which are called the CORE e series. It is composed of a shift-register array to store data, a decoder to select the shift register pointed to by a given address, and mergers to output data. To achieve high density, we introduced a new memory system structure and designed compact storage elements and other peripheral components. We integrated two 256-bit memory systems (32 entries for 8-bit data and instructions each) with a CORE e microprocessor and fabricated it using the National Institute of Advanced Industrial Science and Technology 10-kA/cm 2 Advanced Process. The area occupied by each memory system is 2.69 mm 2 . We obtained correct operations for all of the addresses in low-frequency tests. The typical measured bias margin was 86%-106%.Index Terms-Memory, microprocessors, rapid single-fluxquantum logic (RSFQ), shift registers.

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