Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space

Abstract

Accurately estimating the rare failure rates for nanoscale circuit blocks (e.g., SRAM, DFF, etc.) is a challenging task, especially when the variation space is high-dimensional. In this paper, we propose a novel scaled-sigma sampling (SSS) method to address this technical challenge. The key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation (i.e., sigma) is scaled up. Next, the failure rate is accurately estimated from these scaled random samples by using an analytical model derived from the theorem of "soft maximum". Several circuit examples designed in nanoscale technologies demonstrate that the proposed SSS method achieves superior accuracy over the traditional importance sampling technique when the dimensionality of the variation space is more than a few hundred.

Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method

“…If the result locates in Case 3, the parameter space boundary of this window is taken as the failure boundary. If the result locates in Case 4, the parameter space boundary of this window is calculated by (15) and (16).…”

“…Only the last sampling points are used for the next window statistics. If the statistical result locates in Case 4, the failure boundary is moved by the success rate as (15) and (16).…”

“…There have been several types of methods based on the SPICE simulations for the SRAM analysis [8,9], e.g., (1) importance sampling (IS); (2) extreme value theory; (3) direct boundary search; and (4) spherical coordinates method. Importance sampling is an efficient method for rare event simulation [10][11][12][13][14][15]. In [10], the mixture importance sampling was proposed for statistical analysis.…”

“…In [14], Gibbs sampling method was used to adaptively explore the failure region by sampling a sequence of one-dimensional probability distribution. The scaled-sigma sampling (SSS) was proposed Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi in [15], and the key idea of SSS is to generate random samples from a distorted distribution for which the standard deviation is scaled up. The key and difficulty for the IS success is how to find a good alternative probability density function, and how to find the initial starting point because of the strong non-linear nature of the SRAM cells.…”

Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

“…The first is a novel ultra-compact, analytical model for gate timing characterisation, and the second is a Bayesian learning algorithm for the parameters of the aforementioned timing model using past library characterizations along with a very small set of additional simulations from the target technology. Bayesian approaches were initially introduced in the area of VLSI design for post-Silicon validation and parameter extraction [10]- [15]. The intrinsic simplicity of the proposed timing model combined with the Bayesian learning [16] framework is capable of building very accurate circuit response representations.…”