Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Pons, Marc; Barajas, E.; Mateo, D.; González, José; Moll, Francesc; Rubio, Antonio; Abella, Jaume; Vera, Xavier; Gonzalez, A.F.

doi:10.1109/dtis.2011.5941428

Cited by 5 publications

(3 citation statements)

References 13 publications

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“…In this process a specific category of manufacturing companies, named system design providers (Salonen, 2011), try to give customers an end-to-end solution starting from the design and development processes. In this sense some authors (Pons et al , 2011; Feng et al , 2012; Perols et al , 2013; Goldin and Berry, 2013) propose time-to-market to be a fundamental strategic issue. For other authors, servitisation has to be exported to manufacturing and production processes as well (Klein and Reinhart, 2013).…”

Section: Literature Reviewmentioning

confidence: 99%

Strategies for modern operations management

Chiarini

Vagnoni

2017

BIJ

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Purpose This research enlarges the debate on the operations management strategies pursued by manufacturing companies. The purpose of this paper is to focus on issues concerning servitisation and customisation, enterprise resource planning (ERP) and Lean-agile, supply chain orchestration, corporate social responsibility (CSR) and Lean for design management. Design/methodology/approach A questionnaire of eight questions which stemmed from a literature review was completed by 152 senior operations managers from 120 large European manufacturing companies. Responses were scaled from strongly agree to strongly disagree. The results were tested for reliability using Cronbach’s α test. The questions were tested through a one-sample t-test. Findings The 152 respondents consider servitisation and standardisation to be a trade-off. They consider integration of ERP strategies with Lean and agile systems and customised products/processes to be difficult. Furthermore, suppliers’ orchestration is considered not that suitable for manufacturing companies and suppliers’ CSR performance measurement excessive. By contrast, a CSR internal performance measurement is helpful for increasing sales. The respondents also indicate that there is a lack of Lean tools for design and development processes and Six Sigma is the only strategy for improving quality performance in design and development processes. Research limitations/implications The findings are applicable only to the manufacturing sector. The findings of this research indicate many avenues of research for scholars. Practical implications The findings can be very useful for manufacturing operations managers deciding their future strategies on operations. Originality/value Findings related to servitisation and customisation, ERP and Lean-agile, supply orchestration for manufacturing companies and Lean and agile for product design are original and open a valuable debate.

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Section: Literature Reviewmentioning

confidence: 99%

Strategies for modern operations management

Chiarini

Vagnoni

2017

BIJ

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“…Nevertheless, note that those overheads can be partially mitigated by the fact that VCTA regular circuits tolerate better process variations [5] and that advanced technology nodes can be used for VCTA circuits earlier than for standard cells [10]. Similarly, VCTA-oriented logic synthesis step could further mitigate overheads as well as other VCTA cell implementations which will be the focus of our future work.…”

Section: B Standard Flow Versus Vcta Flowmentioning

confidence: 97%

Design of complex circuits using the Via-Configurable transistor array regular layout fabric

Pons

Moll

Rubio

et al. 2011

2011 IEEE International SOC Conference

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Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.

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“…As the overall chip area was constrained to 1 mm 2 , a trade-off existed between the number of VCDLs and the number of stages per VCDL. As reported in [79], longer delay lines suffer larger local variations (mismatch), at the expense of the statistical population. The number of available silicon dies was 22, and hence, the total VCDL population is 176 for each layout style and transistor size.…”

Section: Demonstrator Chip Descriptionmentioning

confidence: 69%

Monitor amb control strategies to reduce the impact of process variations in digital circuits

Mauricio Ferré

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As CMOS technology scales down, Process, Voltage, Temperature and Ageing (PVTA) variations have an increasing impact on the performance and power consumption of electronic devices. These issues may hold back the continuous improvement of these devices in the near future. There are several ways to face the variability problem: to increase the operating margins of maximum clock frequency, the implementation of lithographic friendly layout styles, and the last one and the focus of this thesis, to adapt the circuit to its actual manufacturing and environment conditions by tuning some of the adjustable parameters once the circuit has been manufactured. The main challenge of this thesis is to develop a low-area variability compensation mechanism to automatically mitigate PVTA variations in run-time, i.e. while integrated circuit is running. This implies the development of a sensor to obtain the most accurate picture of variability, and the implementation of a control block to knob some of the electrical parameters of the circuit. A mesura que la tecnologia CMOS escala, les variacions de Procés, Voltatge, Temperatura i Envelliment (PVTA) tenen un impacte creixent en el rendiment i el consum de potència dels dispositius electrònics. Aquesta problemàtica podria arribar a frenar la millora contínua d'aquests dispositius en un futur proper. Hi ha diverses maneres d'afrontar el problema de la variabilitat: relaxar el marge de la freqüència màxima d'operació, implementar dissenys físics de xips més fàcils de litografiar, i per últim i com a tema principal d'aquesta tesi, adaptar el xip a les condicions de fabricació i d'entorn mitjançant la modificació d'algun dels seus paràmetres ajustables una vegada el circuit ja ha estat fabricat. El principal repte d'aquesta tesi és desenvolupar un mecanisme de compensació de variabilitat per tal de mitigar les variacions PVTA de manera automàtica en temps d'execució, és a dir, mentre el xip està funcionant. Això implica el desenvolupament d'un sensor capaç de mesurar la variabilitat de la manera més acurada possible, i la implementació d'un bloc de control que permeti l'ajust d'alguns dels paràmetres elèctrics dels circuits.

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Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study

Cited by 5 publications

References 13 publications

Strategies for modern operations management

Strategies for modern operations management

Design of complex circuits using the Via-Configurable transistor array regular layout fabric

Monitor amb control strategies to reduce the impact of process variations in digital circuits

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