Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies

Kerber, A.; Wan, Xiongbo; Liu, Yang; Nigam, T.

doi:10.1109/ted.2015.2415414

Cited by 19 publications

(2 citation statements)

References 15 publications

(22 reference statements)

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“…For this purpose, two or more sets of RO-based monitor circuits are deployed: sets of pristine and heavily pre-stressed monitors, as represented in Figure 6 with blue and red ovals [ 30 , 33 ]. To determine the wear-out of the IC as well as to feature the tamper flag capability, our RO-based monitor technology exploits BTI and HCD [ 57 , 58 , 59 , 60 , 61 ] degradation phenomena at the circuit level. When the monitors are operated in static mode, i.e., with an open feedback loop where there is no oscillation, the main degradation mechanism is BTI for regular-RO monitors or with DC HCD degradation in our new True-HCD monitor.…”

Section: The On-chip Degradation Monitor With Tamper-aware Capability...mentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.

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Section: The On-chip Degradation Monitor With Tamper-aware Capability...mentioning

confidence: 99%

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

Diaz-Fortuny,

Saraza-Canflanca,

Bury

et al. 2024

Micromachines

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“…Ring oscillator is widely used in the communication system design especially in the wireless ssystem [1]- [5] and FPGA application [6], [7] because of its wide tuning range, making them more robust over process and temperature variations. It also use used to study the degradation of logic CMOS circuit [8], [9]. Many trade-offs in terms of speed, power, area and application domain need to be considered in designing a ring oscillator.…”

Section: Introductionmentioning

confidence: 99%

CMOS ring oscillator delay cell performance: a comparative study

Hadi¹,

Jidin²,

Wahab³

et al. 2019

IJECE

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A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.

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Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

Kerber

2016

Microelectronics Reliability

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Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies

Cited by 19 publications

References 15 publications

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

An In-Depth Study of Ring Oscillator Reliability under Accelerated Degradation and Annealing to Unveil Integrated Circuit Usage

CMOS ring oscillator delay cell performance: a comparative study

Device to circuit reliability correlations for metal gate/high-k transistors in scaled CMOS technologies

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