Fast WG stream cipher

Krengel, Evgeny I.

doi:10.1109/sibircon.2008.4602594

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…In [22], the authors replaced the inversion operation with a computation of the power 2 k − 1 which requires 4 multiplications for k = 29 3 = 10 and reduced the other seven multiplications of the WG transformation in [13] by one through signal reuse. In [16], the author uses the interleaved approach with pre-computation [12] in order to enhance the speed of the cipher so that it outputs one bit per a clock cycle at the expense of requiring 2 29 bits of ROM for hardware realization. In [17], the authors propose a multiple-bit output version of the WG cipher, called MOWG, which reduces the hardware cost through signal reuse by removing one multiplier from the WG transformation in [22], while it generates d ≤ 17 output bits.…”

Section: Introductionmentioning

confidence: 99%

New Implementations of the WG Stream Cipher

El-Razouk

Reyhani-Masoleh

Gong

2014

IEEE Trans. VLSI Syst.

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This paper presents two new hardware designs of the WG-128 cipher, one for the multiple output version (MOWG), and the other for the single output version (WG), based on type-II optimal normal basis (ONB) representation. The proposed MOWG design uses signal reuse techniques to reduce hardware cost in the MOWG transformation, while it increases the speed by eliminating the inverters from the critical path. This is accomplished through reconstructing the Key and Initial Vector (IV) loading Algorithm (KIA) and the feedback polynomial of the Linear Feedback Shift Register (LFSR). The proposed WG design uses properties of the trace function to optimize the hardware cost in the WG transformation. The ASIC and FPGA implementations of the proposed designs show that their areas and power consumptions outperform the existing implementations of the WG cipher.

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Section: Introductionmentioning

confidence: 99%

New Implementations of the WG Stream Cipher

El-Razouk

Reyhani-Masoleh

Gong

2014

IEEE Trans. VLSI Syst.

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“…Their hardware design has been further improved in [19] by eliminating one multiplier through signal reuse and replacing the inversion with an exponentiation. In [13], Krengel proposed an interleaved approach with precomputation which can achieve an 8-fold speed-up at the cost of 2 29 bits of ROM in hardware. Lam et al [14] presented the hardware design of the MOWG, a multi-bit output variant of the original WG cipher.…”

Section: Introductionmentioning

confidence: 99%

Efficient hardware implementation of the stream cipher WG-16 with composite field arithmetic

Fan

Zidarič

Aagaard

et al. 2013

Proceedings of the 3rd International Workshop on Trustworthy Embedded Devices

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The Welch-Gong (WG) stream cipher family was designed based on the WG transformation and is able to generate keystreams with mathematically proven randomness properties such as long period, balance, ideal tuple distribution, ideal two-level autocorrelation and high and exact linear complexity. In this paper, we present a compact hardware architecture and its pipelined implementation of the stream cipher WG-16, an efficient instance of the WG stream cipher family, using composite field arithmetic and a newly proposed property of the trace function in tower field representation. Instead of using the original binary field F 2 16 , we demonstrate that its isomorphic tower field F (((2 2 ) 2 ) 2 ) 2 can lead to a more efficient hardware implementation. Efficient conversion matrices connecting the binary field F 2 16 and the tower field F (((2 2 ) 2 ) 2 ) 2 are also derived. Our implementation results show that the pipelined WG-16 hardware core can achieve the throughput of 124 MHz at the cost of 478 slices in an FPGA and 552 MHz at the cost of 12, 031 GEs in a 65 nm ASIC, respectively.

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The welch-gong stream cipher - evolutionary path

Zidarič,

Mandal,

Gong

et al. 2023

Cryptogr. Commun.

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This survey presents the rich history of the Welch-Gong (WG) Stream cipher family. It has been a long journey that lead the WG stream ciphers to become practical. The evolutionary path is a combination of mathematical endeavour and engineering striving to transfer pure mathematical functions to practical encryption algorithms for various applications. This path began as the pioneering work on WG transformation sequences with 2-level autocorrelation, leading to important breakthroughs in the early 2000’s, such as the submission of the first WG stream cipher to the eSTREAM competition in 2005 and the subsequent introduction of the WG stream cipher family WG(m, l), followed by extensive work on particular instances proposed for various (mostly lightweight) applications. A recent construction using a WG permutation is the authenticated encryption WAGE, submitted to the NIST LWC competition in 2019. The story of the WG stream cipher is by far not finished. The future opens numerous possibilities for WG stream ciphers and WAGE, with applications in both lightweight environments and in high-performance computing. We conclude the survey with new ideas and open problems.

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Fast WG stream cipher

Cited by 5 publications

References 6 publications

New Implementations of the WG Stream Cipher

New Implementations of the WG Stream Cipher

Efficient hardware implementation of the stream cipher WG-16 with composite field arithmetic

The welch-gong stream cipher - evolutionary path

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