FastCache: A write-optimized edge storage system via concurrent merging cache for IoT applications

Lin, Qian; Qu, Zhihao; Cai, Miao; Ye, Baoliu; Wang, Xiaoliang; Wu, Jianyu; Duan, Weiguo; Zhao, Ming; Lin, Qiang

doi:10.1016/j.sysarc.2022.102718

Cited by 4 publications

(2 citation statements)

References 33 publications

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“…Meanwhile, Sioulas et al [23] designed and implemented a family of novel, partitioning-based GPU-join algorithms that work around the limited memory capacity and slow PCIe interface in GPU. Lin Qian et al [24] designed a write-optimized edge storage system via concurrent microwrites merging. They implement a two-level cache structure that dispatches the concurrent write threads efficiently and significantly mitigates the cache block competition problem with a flexible merging scheme.…”

Section: Hardware-based Equi-join Acceleratormentioning

confidence: 99%

High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA

XUE,

WU,

LUO

et al. 2024

IEICE Trans. Fundamentals

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Join is an important but data-intensive and computeintensive operation in database systems. Moreover, there are multiple types of join operations according to different join conditions and data relationships with diverse complexities. Because most existing solutions for accelerating the join operation on field programmable gate arrays (FPGAs) focus only on the easiest join application, this study presents a novel architecture that is suitable for multiple types of join operation. This architecture has a modular design and consists of three components that are executed sequentially and in pipeline. Specifically, the top-K sorter is used instead of the full sorter to reduce resource utilization and advance the merge processing. Further, the architecture is perfectly compatible with both N-to-1 and N-to-M join relationships, and can also adapt well to both equi-join and band-join. Experimental results show that this design, which is implemented on an FPGA, achieved a high join throughput of 242.1 million tuples per second, which is better than other reported FPGA implementations.

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Section: Hardware-based Equi-join Acceleratormentioning

confidence: 99%

High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA

XUE,

WU,

LUO

et al. 2024

IEICE Trans. Fundamentals

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“…To further improve the FedAM algorithm's performance and efficiency, we incorporated edge caching techniques [53][54][55][56][57][58] and Bayesian optimization for hyperparameter tuning.…”

Section: Incorporating Edge Caching and Bayesian Optimizationsmentioning

confidence: 99%

Federated Edge Intelligence and Edge Caching Mechanisms

Karras

Giotopoulos

et al. 2023

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Federated learning (FL) has emerged as a promising technique for preserving user privacy and ensuring data security in distributed machine learning contexts, particularly in edge intelligence and edge caching applications. Recognizing the prevalent challenges of imbalanced and noisy data impacting scalability and resilience, our study introduces two innovative algorithms crafted for FL within a peer-to-peer framework. These algorithms aim to enhance performance, especially in decentralized and resource-limited settings. Furthermore, we propose a client-balancing Dirichlet sampling algorithm with probabilistic guarantees to mitigate oversampling issues, optimizing data distribution among clients to achieve more accurate and reliable model training. Within the specifics of our study, we employed 10, 20, and 40 Raspberry Pi devices as clients in a practical FL scenario, simulating real-world conditions. The well-known FedAvg algorithm was implemented, enabling multi-epoch client training before weight integration. Additionally, we examined the influence of real-world dataset noise, culminating in a performance analysis that underscores how our novel methods and research significantly advance robust and efficient FL techniques, thereby enhancing the overall effectiveness of decentralized machine learning applications, including edge intelligence and edge caching.

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Resource-aware multi-task offloading and dependency-aware scheduling for integrated edge-enabled IoV

Awada

Zhang

Chen

et al. 2023

Journal of Systems Architecture

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FastCache: A write-optimized edge storage system via concurrent merging cache for IoT applications

Cited by 4 publications

References 33 publications

High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA

High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA

Federated Edge Intelligence and Edge Caching Mechanisms

Resource-aware multi-task offloading and dependency-aware scheduling for integrated edge-enabled IoV

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