Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods

Abstract

This paper proposes two improved interleaved modular multiplication algorithms based on Barrett and Montgomery modular reduction. The algorithms are simple and especially suitable for hardware implementations. Four large sets of moduli for which the proposed methods apply are given and analyzed from a security point of view. By considering state-of-the-art attacks on public-key cryptosystems, we show that the proposed sets are safe to use, in practice, for both elliptic curve cryptography and RSA cryptosystems. We propose a hardware architecture for the modular multiplier that is based on our methods. The results show that concerning the speed, our proposed architecture outperforms the modular multiplier based on standard modular multiplication by more than 50 percent. Additionally, our design consumes less area compared to the standard solutions.

Pipelined modular multiplier supporting multiple standard prime fields

“…In comparison, the latency of the 100-MHz Virtex-6 FPGA implementation of our IMM-based multiplier is 0.08 μs latency for p 256 . However, the maximum throughput of our pipelined multiplier's implementation is 5 times higher than that in [20]. 1 A relatively high throughput of our multiplier can be partly attributed to the use of the fast-reduction NIST prime fields.…”

“…Higher-radix Montgomery multiplier implementations have been reported in [12], [13], [14] (radix-4), [15], [16] (radix-8), [17], [18], [19] (radix-16), [20] (radix-32), [21] (radix-64), and [22] (radix-256). Higher-radix multipliers typically result in faster multiplications, but also require more area than radix-2 multipliers.…”

“…Hardware implementations of different IMM variants have been presented in [23], [24], [25], [11], [20], among which Knezevic et al [20] report the fastest 130-nm 320-MHz ASIC implementation, whose latency is approximately 0.05 μs for 256-bit primes. In comparison, the latency of the 100-MHz Virtex-6 FPGA implementation of our IMM-based multiplier is 0.08 μs latency for p 256 .…”

Faster Interleaved Modular Multiplier Based on Sign Detection

“…Modified interleaved modular multiplication [1]. MIMM computes modular multiplication without a pre-computational phase, or predefined sets for moduli [1,9].…”

Evaluation of Large Integer Multiplication Methods on Hardware

“…Modular multiplication has been investigated and Montgomery multipliers have been optimised for use in public key cryptography [17], [19]- [21]. An analysis of the hardware complexity of several multipliers for modular multiplication and modular exponentiation for use in public key cryptography has shown Karatsuba outperforms traditional schoolbook multiplication for operands greater than or equal to 32 bits [17].…”