Faster Pairing Coprocessor Architecture

Abstract

In this paper, we present a high-speed pairing coprocessor using Residue Number System (RNS) which is intrinsically suitable for parallel computation. This work improves the design of Cheung et al. [11] using a carefully selected RNS base and an optimized pipeline design of the modular multiplier. As a result, the cycle count for a modular reduction has been halved. When combining with the lazy reduction, Karatsuba-like formulas and optimal pipeline scheduling, a 128-bit optimal ate pairing computation can be completed in less than 100,000 cycles. We prototype the design on a Xilinx Virtex-6 FPGA using 5237 slices and 64 DSPs; a 128-bit pairing is computed in 0.358 ms running at 230MHz. To the best of our knowledge, this implementation outperforms all reported hardware and software designs.

Novel RNS Parameter Selection for Fast Modular Multiplication

“…In our previous work [12], [16], we observe that the complexity of BE can be reduced if the moduli in the two bases are close to each other. The BE step, (5), can be written as a matrix-by-vector multiplication followed by channel reductions.…”

“…We used the proposed method to select parameters for pairing implementations on FPGA [12], [16]. The CoxRower architecture have been used in these works, and a 256-bit modulo operation is reduced from 19 cycles to 5 cycles on the similar hardware architecture.…”

“…However, the optimal parameter is n 4 for rlog 2 P s 256 and m 18 (the FPGA has premounted 18-bit multipliers). Therefore, our following work [16] chooses n 4 and w 67, and one modular reduction only takes 6 cycles. With precomputations as Algorithm 3, it can be further reduced to 5 cycles on the same architecture as [16].…”

“…Therefore, our following work [16] chooses n 4 and w 67, and one modular reduction only takes 6 cycles. With precomputations as Algorithm 3, it can be further reduced to 5 cycles on the same architecture as [16]. The implementation details are out of the scope of this paper.…”

Implementing Complete Formulas on Weierstrass Curves in Hardware

“…The design is based on Residue Number System (RNS), facilitating carry-free arithmetic and parallelism. Yao et al [40] followed the idea of using RNS to design a high-speed ECC co-processor for pairings. Sakiyama et al [35] proposed a superscalar coprocessor that could deal with three different curve-based cryptosystems, all in characteristic 2 fields.…”