Fault Collapsing for Flash Memory Disturb Faults

Mohammad, M.G.; Terkawi, L.

doi:10.1109/ets.2005.24

Cited by 7 publications

(7 citation statements)

References 16 publications

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“…In a split-gate cell, the channel of the transistor is split and overlapped by two distinct gates, i.e., FG and CG. In general, the stacked-gate cell is called a 1T cell, and the split-gate cell is called a 1.5T cell [21]. Because the split-gate cell can inhibit punchthrough on the unselected rows and prevents leakage current on the BL, the BL disturb faults and over-erase disturb faults are not likely to occur.…”

Section: Functional Fault Modelsmentioning

confidence: 99%

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Yeh

Cheng

Chou

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the systemon-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, costeffective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit-or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism.Index Terms-Built-in self-diagnosis (BISD), built-in self-test (BIST), fault diagnosis, flash memory, March-like test, memory testing.

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Section: Functional Fault Modelsmentioning

confidence: 99%

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Yeh

Cheng

Chou

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Then, the reduced fault lists can be used to develop more efficient test algorithms. In [8], however, only the impact of the cell structure and array type (NAND or NOR array) on the disturbance faults is discussed.…”

Section: Introductionmentioning

confidence: 99%

“…In [8], Mohammad and Terkawi presents the fault collapsing concept for disturbance faults of flash memories. The reduced fault lists of flash memories with various cell structures (i.e., 1T or 1.5T cell) and array types (i.e., NAND or NOR array) are different.…”

Section: Introductionmentioning

confidence: 99%

Testing Disturbance Faults in Various NAND Flash Memories

Hou

2013

2013 22nd Asian Test Symposium

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NAND flash memory is the most popular nonvolatile memory. Due to the specific mechanism of functional operations, flash memories are prone to disturbance faults. Furthermore, different NAND flash memories might have some differences on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are developed.

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“…In [12], Mohammad and Terkawi present the fault collapsing concept for disturbance faults of flash memories. The reduced fault lists of flash memories with various cell structures (i.e., 1 T or 1.5 T cell) and array types (i.e., NAND or NOR array) are different.…”

mentioning

confidence: 99%

“…Then, the reduced fault lists can be used to develop more efficient test algorithms. In [12], however, only the impact of the cell structure and array type (NAND or NOR array) on the disturbance faults is discussed.…”

mentioning

confidence: 99%

Testing Disturbance Faults in Various NAND Flash Memories

Hou¹,

Li²

2014

J Electron Test

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NAND flash memory is one popular non-volatile memory. Flash memory is prone to disturbance faults due to its specific mechanism of functional operations. Furthermore, different NAND flash memories might be different on the array organizations and the supported functional operations. For example, some NAND flash memories can support the random program operation, but some cannot; some NAND flash memories with single-page wordlines and some with multiple-page wordlines. The differences on the array organizations and the functional operations result in the heavy influence on the testing of disturbance faults. In this paper, therefore, we analyze the disturbance faults for NAND flash memories with different array organizations and functional operations. Also, test algorithms for covering the disturbance faults in various types of NAND flash memories are proposed.

show abstract

Fault Collapsing for Flash Memory Disturb Faults

Cited by 7 publications

References 16 publications

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Testing Disturbance Faults in Various NAND Flash Memories

Testing Disturbance Faults in Various NAND Flash Memories

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