Fault Detection and Analysis in embedded SRAM for sub nanometer technology

Maddela, Venkatesham; Sinha, Sanjeet Kumar; Parvathi, Muddapu; Vp, Sharma

doi:10.1109/icaaic53929.2022.9793265

Cited by 6 publications

(2 citation statements)

References 15 publications

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“…The system experiences different impacts depending on how short or open defects between the nodes. The effect of such short/open faults on the behavior of deep submicron 6T-SRAM cells is explored in this work [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning

Maddela,

Sinha,

Parvathi

et al. 2024

Preprint

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In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. Many fault models have developed, however their flexibility of use is limited by the restrictions and constraints of the provided test environment. The majority of existing fault models have been studied in terms of well-known March algorithms, which simply provide fault detection information. Scaled-down technologies have an impact on parasitic effects as well, resulting in an extra source of defective behavior and making current test algorithms vulnerable to them. Recent work that uses method of parasitic extraction for fault detection have addressed the problem of limitation due to scale down technologies. However, as the circuit complexity increases the estimation of RC would be tedious. Hence in this paper machine learning based parasitic RC extraction is proposed. Also, as an extension to that, proposed ML based fault detection using extracted parasitic RCs as dataset. The proposed machine learning based fault prediction uses extracted parasitic RCs as dataset. The parasitic RC values are extracted for each fault model using technologies of 120nm down to deep submicron 7nm. Regression algorithm is used for modeling the machine for extraction of RCs and observed that 88% of prediction accuracy. Decision tree modeling is used for fault detection and observed 91.7% of accuracy in prediction of fault. 3.1 Effect of open defects in 6T SRAM Cell In this are article we have consider the node to node open/short faults. In Fig 2. We have imposed all possible open defects and then we have analyzed the memory cell for all possible open defects. There are totally 25 open defects are possible as shown in the fig 2. The simulation results and different types faults occurs for all open defects are shown in table 1 Fig2: Fault model for Open Defects in 6T-SRAM Cell Table 1. 6T SRAM Cell open defect list for different technologies

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Section: Introductionmentioning

confidence: 99%

Parasitic RC Estimation and Defect Prediction for Embedded Memory using Machine Learning

Maddela,

Sinha,

Parvathi

et al. 2024

Preprint

Self Cite

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“…This parasitic effect causes additional faults, which are not detected by the existing test methods. [8,16,19,21] Proposed a new parasitic extraction method that gives fault coverage with fault location. Resistive-opens/shorts falls [10][11][12][13][14][15] are timing-dependent fault models.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of Open and Short Defects in Embedded SRAM Using Parasitic Extraction Method for Deep Submicron Technology

Maddela,

Sinha,

Parvathi

et al. 2023

Wireless Pers Commun

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The technology advances from the micron level to the Nanometer level. This striking change in the technology with so many factors might in uence the embedded device design and its performance. In the fast-growing technology, it is very di cult to nd suitable algorithms to test embedded SRAM. It is noticed that while going to deep sub-nano technologies, the existing test methods may not fully satisfy the test results due to the increased number of faults and defects. Scale-down technologies have an impact on the parasitic effects, creating an additional source of faulty behavior, and making the existing test techniques less effective in detecting them. In this paper we propose a new method, taking the parasitic effect into the consideration, which gives the fault information along with its location. In the proposed method we have considered node-to-node open and short defects for different technologies (45nm, 32nm, and 7nm). It is observed that the proposed test method gives 100% fault coverage which is independent of technology variation.

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