Fault injection analysis of transient faults in clustered VLIW processors

Sterpone, Luca; Sabena, Davide; Campagna, Salvatore; Reorda, M. Sonza

doi:10.1109/ddecs.2011.5783081

Cited by 4 publications

(6 citation statements)

References 8 publications

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“…Clearly, if any of the three result is wrong, the TMR can detect and mask the fault. However, as we explained in the previous section, the presence in the VLIW behavior of crossdomain faults can cause this kind of hardening technique to fail [18].…”

Section: The Proposed Methodsmentioning

confidence: 99%

“…The purpose of this step is to check the effectiveness of the TMR hardening technique, when applied at software level and running on a VLIW processor, and to detect the critical points that need to be modified in order to increase the soft-error fault tolerance. As we reported in [18], sometimes the SIHFT technique based on TMR and implemented at the C code level are not able to cope with all the failures affecting the user logic resources. This purpose has been accomplished by the creation of an algorithm able to identify the specific effects intrinsic of the VLIW software compiler rules.…”

Section: Introductionmentioning

confidence: 94%

“…In [18] we presented a detailed analysis of a software hardening technique applied to the high-level instruction code of a VLIW processor in order to mitigate the effect of the transient faults. In particular, the work in [18] presents the results of a preliminary investigation on the effects of transient faults happening in the VLIW datapath when different software protection techniques based on Triple Modular Redundancy are used.…”

Section: Related Workmentioning

confidence: 99%

“…In particular, the work in [18] presents the results of a preliminary investigation on the effects of transient faults happening in the VLIW datapath when different software protection techniques based on Triple Modular Redundancy are used.…”

Section: Related Workmentioning

confidence: 99%

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Soft error effects analysis and mitigation in VLIW safety-critical applications

Sabena

Reorda

Sterpone

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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VLIW architectures are widely employed in several embedded signal applications since they offer the opportunity to obtain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors are being considered for employment in various embedded processing systems, including safety-critical ones (e.g., in the aerospace, automotive and rail transport domains). Terrestrial safety-critical applications based on newer nano-scale technologies raise increasing concerns about transient errors induced by neutrons. Therefore, techniques to effectively estimate and improve the reliability of VLIW processors are of great interest. In this paper, we present a novel technique aimed to further improve the efficiency of the Triple Modular Redundancy (TMR) hardening-technique applied at the software level on VLIW processors. In particular, we first experimentally demonstrate that the TMR-based software technique, when applied at the C code level, is not able to cope with most of the failures affecting user logic resources. Then, we propose a method able to analyze and modify the TMR-based code for a generic VLIW processor in order to improve the fault tolerance of the executed application without modifying the VLIW processor. In details, the proposed technique is able to reduce the number of cross-domain errors affecting the TMR-hardened code of a VLIW processor data path. We provide figures about performance and fault coverage for both the unprotected and protected versions of a set of benchmark applications, thus demonstrating the benefits and limitations of our approach.Index Terms-Hardening technique, VLIW processor, cross domain error.

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Section: The Proposed Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 94%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Soft error effects analysis and mitigation in VLIW safety-critical applications

Sabena

Reorda

Sterpone

2014

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

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“…The fault injection is simulated in ModelSim and emulated on an FPGA with a linear feedback shift register (LFSR). The Very Long Instruction Word processor r-VEX is implemented on an FPGA and faults are injected into the instruction register, the register file and the SRAM of the processor by Sterpone et al [9]. Sartori et al [10] Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Identification of critical variables using an FPGA-based fault injection framework

Riefert

Müller

Sauer

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract-The shrinking nanometer technologies of modern microprocessors and the aggressive supply voltage down-scaling drastically increase the risk of soft errors. In order to cope with this risk efficiently, selective hardware and software protection schemes are applied. In this paper, we propose an FPGA-based fault injection framework which is able to identify the most critical registers of an entire microprocessor. Furthermore, our framework identifies critical variables in the source code of an arbitrary application running in its native environment. We verify the feasibility and relevance of our approach by implementing a lightweight and efficient error correction mechanism protecting only the most critical parts of the system. Experimental results with state estimation applications demonstrate a significantly reduced number of critical calculation errors caused by faults injected into the processor.

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