Fault injection and failure analysis on Xilinx 16 nm FinFET Ultrascale+ MPSoC

Wu, Yang; Li, Yonghong; He, Chaohui

doi:10.1016/j.net.2021.12.022

Cited by 6 publications

(3 citation statements)

References 16 publications

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“…The works [33][34][35][36][37][38] present similar platforms for fault injection in CUT (or DUT) and can be used for the same purpose and also make use of the ICAP port for the injection of the faults. However, the works listed focus on evaluating the sensitivity to SEEs of SRAM-based FPGAs, not being focused on CUT.…”

Section: Related Workmentioning

confidence: 99%

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

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Section: Related Workmentioning

confidence: 99%

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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“…Additionally, the necessary bits are activated in the constraints. After synthesis and implementation, the bitstream and essential bit files, including essential bit data (EBD) and essential bit configuration (EBC) files, can be obtained [39,40]; • FI Script creation: The FI script is created by extracting a total of 50,000 intended injected bits from the EBD file for each DNN. In the EBD file, the '1 bits represent the essential bits.…”

Section: Fi Designmentioning

confidence: 99%

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset

Yang,

Song,

Guo

et al. 2023

Micromachines

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This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform.

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“…Once this confirmation is established, greater emphasis and effort are placed on software fault injection. Compared to irradiation testing, software fault injection allows for more detailed insights that may be challenging to extract solely through irradiation [29]. Additionally, the fault injection technique relies on the results of Monte Carlo simulations, which utilize models constructed from the tested chip.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of Single Event Upset on a Relay Protection Device

Zhou,

Yu,

Zou

et al. 2023

Electronics

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Traditionally, studies have primarily focused on single event effects in aerospace electronics. However, current research has confirmed that atmospheric neutrons can also induce single event effects in China’s advanced technology relay protection devices. Spallation neutron irradiation tests on a Loongson 2K1000 system-on-chip based relay protection device have revealed soft errors, including abnormal sampling, refusal of operation and interlock in the relay protection device. Given the absence of standardized evaluation methods for single event effects on relay protection devices, the following research emphasizes the use of Monte Carlo simulation and software fault injection. Various types of single event upsets, such as single bit upsets, dual bit upsets, and even eight bit upsets, were observed in Monte Carlo simulations where atmospheric neutrons hit the chip from different directions (top and bottom). The simulation results indicated that the single event effect sensitivity of the relay protection device was similar whether the neutron hit from the top or the bottom. Through software fault injection, the study also identified soft errors caused by neutron induced single event upsets on the Loongson 2K1000 system, including failure to execute, system halt, time out, and error result. And the soft error number of system halts and error results exceeded that of time outs and failures to execute in all three tested programs. This research represents a preliminary assessment of single event effects on relay protection devices and is expected to provide valuable insights for evaluating the reliability of advanced technology relay protection devices.

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Fault injection and failure analysis on Xilinx 16 nm FinFET Ultrascale+ MPSoC

Cited by 6 publications

References 16 publications

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

Enhancement of Deep Neural Network Recognition on MPSoC with Single Event Upset

Evaluation of Single Event Upset on a Relay Protection Device

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