Fault injection into VHDL models: the MEFISTO tool

Jenn, Éric; Arlat, Jean; Rimen, M.; Ohlsson, J.; Karlsson, Johan

doi:10.1109/ftcs.1994.315656

Cited by 290 publications

(125 citation statements)

References 9 publications

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“…The simulation-based fault injection technique uses the VHDL model as the target system, and it usually includes two implementation methods: modifying the VHDL model and altering the value of signals and variables defined in the prototype [9].…”

Section: Related Workmentioning

confidence: 99%

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A Simulation-based Fault Injection Mechanism of Digital Circuit

2017

The 5th International Conference on Advanced Computer Science Applications and Technologies (ACSAT 2017)

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Abstract. Fault injection is a key step in the validation of fault-tolerant design. This paper introduces a novel simulation-based fault injection method. The proposed method is implemented directly in Test Bench (TB) by modifying the signal values in VHDL model, and the fault type and ratio, transient fault duration and fault injection rate etc. can be easily adjusted according to requirements. It also supports the random fault injection by giving a random distribution. Compared with existing approaches, this simple method that can be designed and used immediately has a better extendibility and a better tailing capability due to the fact that it is field programmable in TB. Fault injection experiment shows that this approach is flexible and easy to use.

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Section: Related Workmentioning

confidence: 99%

“…It is necessary to add two kinds of dedicated components called "saboteur" and "mutant" which are usually inactive during normal system operation and activated only to inject faults [7], [8], [9], [10]. A saboteur is a special VHDL component added to the original model.…”

Section: Related Workmentioning

confidence: 99%

A Simulation-based Fault Injection Mechanism of Digital Circuit

2017

The 5th International Conference on Advanced Computer Science Applications and Technologies (ACSAT 2017)

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“…Similar to some fault injection campaigns [4][5], we are basing our description of design error models on three basic characteristics: i) the activation criteria, ii) the consequence of activation, and iii) error injection. Multiple design errors are simulated concurrently; therefore each design error has a unique identification number.…”

Section: Abstract Design-error Modelsmentioning

confidence: 99%

Mutation-based validation of high-level microprocessor implementations

Campos

Al-Asaad

2004

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

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“…Several fault injection techniques have been proposed in the past decades; they can be categorized into simulationbased techniques [4] [5] [6] [7] [8], software-implemented techniques [9] [10] [11] [12], hardware-based techniques [13] [14] [15], and test port-based techniques [8] [12] [16] [17].…”

Section: Introductionmentioning

confidence: 99%

Light-Weight Techniques for Improving the Controllability and Efficiency of ISA-Level Fault Injection Tools

Sangchoolie

Johansson

Karlsson

2017

2017 IEEE 22nd Pacific Rim International Symposium on Dependable Computing (PRDC)

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Abstract-ISA-level fault injection, i.e. the injection of bitflip faults in Instruction Set Architecture (ISA) registers and main memory words, is widely used for studying the impact of transient and intermittent hardware faults. ISA-level fault injection tools can be characterized by different properties such as repeatability, observability, reachability, intrusiveness, efficiency and controllability. This paper presents two preinjection analysis techniques that improve controllability and efficiency using object code analysis. To improve controllability, we propose a technique for identifying the type of data that is stored in a potential target location. This allows the user to selectively direct fault injections to addresses, data and/or control information. Experimental results show that the data type of 84-100% of the targets locations in 8 programs were successfully identified by this technique. The second technique improves efficiency by fault pruning, i.e., by avoiding injection of faults that is known a priori to be detected by the tested system. This technique leverage the fact that faults in certain bits in the program counter and the stack pointer are always detected by machine exceptions. We show that exclusion of these bits from the fault space could significantly prune the fault space and reduce the time it takes to conduct a fault injection campaign.

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Fault injection into VHDL models: the MEFISTO tool

Cited by 290 publications

References 9 publications

A Simulation-based Fault Injection Mechanism of Digital Circuit

A Simulation-based Fault Injection Mechanism of Digital Circuit

Mutation-based validation of high-level microprocessor implementations

Light-Weight Techniques for Improving the Controllability and Efficiency of ISA-Level Fault Injection Tools

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