Fault Localizing End-to-End Flow Control Protocol for Networks-on-Chip

Schley, Gert; Batzolis, N.; Radetzki, Marian

doi:10.1109/pdp.2013.74

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…For this purpose, a scoreboard-based mechanism has been suggested [30] that narrows down fault location by using statistics of faults occurred on multiple transmission paths: Those network resources present in a maximal number of faulty paths are likely fault candidates. To overcome the probabilistic nature of this approach, we have proposed a bisection mechanism [28] to iteratively narrow down fault location to a single switch, using a single transmission path.…”

Section: Diagnostic Protocolmentioning

confidence: 99%

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Multi-Layer Test and Diagnosis for Dependable NoCs

Wunderlich

Radetzki

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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Networks-on-chip are inherently fault tolerant or at least gracefully degradable as both, connectivity and amount of resources, provide some useful redundancy. These properties can only be exploited extensively if test and diagnosis techniques support fault detection and error containment in an optimized way. On the one hand, all faulty components have to be isolated, and on the other hand, remaining faultfree functionalities have to be kept operational. In this contribution, behavioral end-to-end error detection is considered together with functional test methods for switches and gate level diagnosis to locate and to isolate faults in the network in an efficient way with low time overhead.

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Section: Diagnostic Protocolmentioning

confidence: 99%

“…For this purpose, information about the identified fault location would have to be passed down the layer hierarchy. In [28] we use a software re-routing approach that is implemented on the transport layer only.…”

Section: Fault-tolerant Routingmentioning

confidence: 99%

Multi-Layer Test and Diagnosis for Dependable NoCs

Wunderlich

Radetzki

2015

Proceedings of the 9th International Symposium on Networks-on-Chip

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“…Then packet has to remap once again which leads to performance degradation. These local faults [4] may occur during the fabrication process or down the length of year of usage. Hence there is a demand to create awareness of local fault in NoC before mapping any packet into any of the node in the network [5].…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of secured agent based NoC using shortest path routing algorithm

S¹,

Jatti²,

Batra³

2019

IJECE

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Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.

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