Fault Rate Analysis: Breaking Masked AES Hardware Implementations Efficiently

Wang, An; Chen, Man; Wang, Zongyue; Wang, Xiaoyun

doi:10.1109/tcsii.2013.2268379

Cited by 23 publications

(17 citation statements)

References 5 publications

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“…Each PUF response requires multiple runs (realizations n) of chaotic system iterations (m). Therefore, each PUF response requires m × r iterations, where each m'th iteration length results from the corresponding SCRO frequency (1). It is obvious that each PUF response requires a 2mr…”

Section: Testing and Resultsmentioning

confidence: 99%

“…Modern cryptography is facing progressively more attacks directed not on cryptographic algorithms, but on their implementations-even the secured ones [1]. Among many kinds of sidechannel attacks (SCAs), there are various ways of retrieving information from memories, where the cryptographic keys are kept [2,3], and therefore there is a struggle for securing the memories against SCAs [4].…”

Section: Introductionmentioning

confidence: 99%

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Chaos-Based Physical Unclonable Functions

Gołofit

Wieczorek

2019

Applied Sciences

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The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

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Section: Testing and Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Chaos-Based Physical Unclonable Functions

Gołofit

Wieczorek

2019

Applied Sciences

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“…It is also known as Fault Rate Analysis. In this attack, clock glitch is inject into the masked S-Box to recover the secret key [46]. A Low complexity attack can be done on AES upto four round using three known plaintext and it can also increased to six round [47].…”

Section: Attacks and Countermeasure (If Possible)mentioning

confidence: 99%

A Survey on Advanced Encryption Standard

2017

IJSR

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“…In CHES 2011, Moradi et al combined correlation-enhanced collision attack [15] with fault sensitivity analysis, and gave new collision attack on two masked S-boxes of AES hardware implementation by colliding timing characteristics [16]. In 2013, the fault rate induced by the clock glitch is employed for collision detection on masked AES S-boxes [17]. Soon after, some other models are discussed [18,19].…”

Section: Introductionmentioning

confidence: 99%

Right or wrong collision rate analysis without profiling: full-automatic collision fault attack

Wang

Tian

Wang

et al. 2017

Sci. China Inf. Sci.

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In CHES 2010, Fault Sensitivity Analysis (FSA) on Advanced Encryption Standard (AES) hardware circuit based on S-box setup-time acquired by injecting clock glitches is proposed. Soon after, some improvements of FSA were presented such as colliding timing characteristics from Moradi et al. However, the acquisition of timing characteristics requires complex procedure due to the very gradual decrease of clock glitch cycle and the heavy requirements of setup-time samples. In HOST 2015, Wang et al. presented template-based right or wrong collision rate attack to improve the efficiency of FSA, but its profiling and plaintexts-choice procedures required too many encryptions. In this paper, we fix only one specific clock glitch cycle, and take the right or wrong collision rate as a collision distinguisher. So, the whole process is a non-profiling collision attack which can be executed automatically without massive pre-computations and interactions between PC and signal generator. According to the experiments, 256 encryptions are enough for exactly deciding whether two plaintext bytes can induce an S-box collision. Compared with the existing power analysis and FSA-based attacks on AES hardware, it costs negligible time (about 6.65 s) and storage space (only one byte), and no offline computations for finding the collision between two masked S-boxes. Furthermore, our study shows that the signal-to-noise ratio in FSA-based attacks is much higher than power-based attacks.

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Fault Rate Analysis: Breaking Masked AES Hardware Implementations Efficiently

Cited by 23 publications

References 5 publications

Chaos-Based Physical Unclonable Functions

Chaos-Based Physical Unclonable Functions

A Survey on Advanced Encryption Standard

Right or wrong collision rate analysis without profiling: full-automatic collision fault attack

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