Fault Simulation and Fault Injection Technology Based on SystemC

Abstract

Electronic systems are essential parts in the everyday life, and these systems have grown continuously in their performance and in their complexity. Therefore, the design process for such a system has also become more and more complex and has become a critical challenge. A popular tool for solving the design process of complex systems is SystemC. SystemC is a C++ language class library, which allows the modeling of hardware behavior in a programming language for software. Advantages by the usage of SystemC are e.g. an integrative concept of the design description in a continuous design flow, combined with a fast execution of compiled code during the simulation process. This chapter describes the simulation of faults in electronic systems by the usage of SystemC. It treats especially faults in hardware, which can occur after a successful validation of the design. The simulation of faults is well known in two operation areas. One field is the fault simulation of test pattern for the detection of fabrication faults. The other field is the simulated fault injection that the effects of faults emerging during the operation of the device. Such procedures are important for analysis of electronic system designs for safety critical applications with respect to their dependability under fault conditions. At first, the chapter explains some issues in the context of fault injection and fault simulation. Furthermore, it relates something about SystemC and the possibility to simulate the design. State of the art applications are also presented for this purpose. A prerequisite for a simulation is an appropriate modeling. The modeling of faults is presented in the context of their design level. It is also shown how a simulation with fault models can be implemented by several injection techniques. In addition, the advantages and disadvantages of the injection techniques are explained. Another challenge for a simulation task is the execution in an acceptable amount of time. Approaches are presented, which help to speed up simulations. Some practical simulation environments are shown at the end of the chapter.

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

“…Fault simulation and fault injection approaches are the most widely used techniques for confirming the functionality of Register Transfer Level (RTL) design and provide an approach to check the quality of test-benches and test patterns [1]. In the design environment, fault simulation is also practised for validation of test quality [2], [3]. By definition, fault simulation is the technique used to simulate a design in the presence of faults.…”