Fault Tolerance in Binary Tree Architectures

Raghavendra,; AVIvizienis,; Ercegovac,

doi:10.1109/tc.1984.1676483

Cited by 114 publications

(25 citation statements)

References 5 publications

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“…However, by observing that there are two redundant links per node at the leaves, which equates to the two father-to-son links of nodes at upper levels, it is evident that the number of pins per chip at the lower levels will be less for chips containing leaf processors. While the implication is that a SOFT tree will require at least two different kinds of chips, the same may be true for modular sparing approaches such as [7,8], or even nonredundant trees if the tree has an odd number of levels.…”

Section: ) M Ultichip Treesmentioning

confidence: 99%

“…in a group of nodes which have been allocated a single spare [7,8]. Unreconfigurable multiple The SS of a spare s is 1 if and only if s is fault free and not configured into the array, or, the nonassociated spare of the SST has SS of 1 and is not configured into the array as a son of s 's associated SST, or s is faulty, and the SST for which s is not associated has SS of 1.…”

Section: ) Analysis O F Reconfigurabilitymentioning

confidence: 99%

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Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance

Lowrie

Fuchs

1987

IEEE Trans. Comput.

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Section: ) M Ultichip Treesmentioning

confidence: 99%

Section: ) Analysis O F Reconfigurabilitymentioning

confidence: 99%

Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance

Lowrie

Fuchs

1987

IEEE Trans. Comput.

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Section: Introductionmentioning

confidence: 99%

“…One is to gracefully degrade the performance of the system [9], the other is the so-called structure fault tolerance. In systems with structure fault tolerance, rigid topology is maintained through redundant spare element replacements caused by the detection of faults [3] [9] [10] [11] [12] [13]. There are two extreme approaches of utilizing the spare during the system reconfiguration phase: global [8] [13] and local reconfiguration [8].…”

Section: Introductionmentioning

confidence: 99%

A dynamic fault-tolerant mesh architecture

Huang

Yang

1999

Lecture Notes in Computer Science

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Abstract.A desired mesh architecture, based on connected-cycle modules, is constructed. To enhance the reliability, multiple bus sets and spare nodes are dynamically inserted to construct modular blocks. Two reconfiguration schemes are associated, and can eliminate the spare substitution domino effect. Simulations show that both schemes provide for increase in reliability over the interstitial redundancy scheme[11] and the multi-level fault tolerance mesh(MFTM) [6], at the same redundant spare ratio. Especially, with global reconfiguration, the reliability improvement ratio per spare (RIPS) can be at least twice of that of the MFTM scheme. Furthermore, the lower port complexity in spare nodes as compared to those in both of the aforementioned schemes, and versatility in reconfiguration capability are two additional merits of our proposed architecture.

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“…A number of researchers have proposed various design methods for structural fault tolerance in multiprocessors, for example, [2], [4], [5], [6], [7], [8], [10], [11], [12], [13], [14], [15], [19], [22], [23], [24], [25], [26], [27], [28]. Most of this work has dealt with the design of deterministic k-faulttolerant (k-FT) multiprocessors in which there are k or more spare processors, and the link and switch complexity is high enough to tolerate any k processor failures (but not more than k processor failures) [2], [4], [5], [6], [7], [8], [10], [11], [12], [13], [14], [15], [19], [27], [23], [24].…”

Section: Introductionmentioning

confidence: 99%

Node covering, error correcting codes and multiprocessors with very high average fault tolerance

Dutt

Mahapatra

Twenty-Fifth International Symposium on Fault-Tolerant Computing. Digest of Papers

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Abstract-Structural fault tolerance (SFT)is the ability of a multiprocessor to reconfigure around faulty processors or links in order to preserve its original processor interconnection structure. In this paper, we focus on the design of SFT multiprocessors that have low switch and link overheads, but can tolerate a very large number of processor faults on the average. Most previous work has concentrated on deterministic k-fault-tolerant (k-FT) designs in which exactly k spare processors and some spare switches and links are added to construct multiprocessors that can tolerate any k processor faults. However, after k faults are reconfigured around, much of the extra links and switches can remain unutilized. It is possible within the basic node-covering framework, which was introduced by Dutt and Hayes as an efficient k-FT design method, to design FT multiprocessors that have the same amount of switches and links as, say, a two-FT deterministic design, but have s spare processors, where s ( 2, so that, on the average, k = Q(s) (k £ s) processor failures can be reconfigured around. Such designs utilize the spare link and switch capacity very efficiently, and are called probabilistic FT designs. An elegant and powerful method to construct covering graphs or CG's, which are key to obtaining the probabilistic FT designs, is to use linear error-correcting codes (ECCs). We show how to construct probabilistic designs with very high average fault tolerance but low wiring and switch overhead using ECCs like the 2D-parity, full-two, 3D-parity, and full-three codes. This design methodology is applicable to any multiprocessor interconnection topology and the resulting FT designs have the same node degree as the non-FT target topology. We also analyze the deterministic fault tolerance for these designs and develop efficient layout strategies for them. Finally, we compare the proposed probabilistic designs to some of the best deterministic and probabilistic designs proposed in the past, and show that our designs can meet a given mean-time-to-failure (MTTF) specification at much lower hardware costs (switch complexity, redundant wiring area, and spare-processor overhead) than previous designs. Further, for a given number of spare processors, our designs have close-to-optimal reconfigurabilities that are much better than those of previous probabilistic designs.

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Fault Tolerance in Binary Tree Architectures

Cited by 114 publications

References 5 publications

Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance

Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance

A dynamic fault-tolerant mesh architecture

Node covering, error correcting codes and multiprocessors with very high average fault tolerance

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