2019
DOI: 10.3233/jhs-190618
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Fault tolerant and congestion aware routing algorithm for network on chip1

Abstract: Continuous technology scaling in semiconductor industry makes the system reliability as a serious concern in the area of nanoscale computing. In this paper, a fully adaptive routing algorithm is proposed to overcome faults in NoCs (Network-on-Chip). This algorithm called DINRA-NoC (DIstiributed and New Routing Algorithm for NoC) is distributed, fault tolerant and congestion-aware. First, each node selects the appropriate output to route packets to neighbor routers according to the state of each link and router… Show more

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Cited by 3 publications
(1 citation statement)
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“…Adaptive Q learning shows 41% lesser delay and 51% more residual energy compared to other methods (Alarifi, A. et al, 2019). Faults in network on chip (NoCs) are addressed using distributed and adaptive routing algorithms (Nehnouh, C. et al, 2019). This method is deadlock free and does not use any virtual channels or routes.…”
Section: Introductionmentioning
confidence: 99%
“…Adaptive Q learning shows 41% lesser delay and 51% more residual energy compared to other methods (Alarifi, A. et al, 2019). Faults in network on chip (NoCs) are addressed using distributed and adaptive routing algorithms (Nehnouh, C. et al, 2019). This method is deadlock free and does not use any virtual channels or routes.…”
Section: Introductionmentioning
confidence: 99%