Fault-tolerant quantum reversible full adder/subtractor: Design and implementation

Mirizadeh, Seyyed Mohammad Amir; Asghari, Parvaneh

doi:10.1016/j.ijleo.2021.168543

Cited by 7 publications

(4 citation statements)

References 25 publications

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“…Feynman gate (Hadamard gate): Feynman gates, or Hadamard gates, create superposition and are employed in a wide range of quantum algorithms, including quantum search algorithms like Grover's algorithm [94][95][96][97].…”

Section: Applications Of Reversible Logic Gatesmentioning

confidence: 99%

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Tiwari,

Kadam,

Dudhedia

et al. 2024

MMEP

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In recent years, reversible logic gates have garnered significant interest because of their potential to decrease energy consumption and meet the growing need for low-power computing systems. Unlike conventional logic gates, reversible logic gates ensure that no information loss happens during computation, allowing for the reversal of the entire computation process. This unique characteristic opens up new avenues for developing energy-efficient digital circuits. This review paper serves as a vital contribution to the field by addressing a noticeable gap in the existing literature regarding reversible logic gates. The study not only comprehensively analyzes the array of reversible logic gates available but also underscores their practical applications and significance. It encompasses a wide variety of reversible logic gates, including Toffoli gates, Fredkin gates, and newer innovations. It is found that Toffoli gates outperformed in terms of gate count and quantum cost reduction, making them a preferred choice for quantum circuit optimization. Additionally, Fredkin gates showed exceptional performance in specific applications, like data swapping and quantum state control. The digital circuits like adders, multiplexers, ALU etc. are successfully designed using reversible gates like HNG, DKG etc. The significant gap this study fills lies in the need for a consolidated and in-depth analysis of the state-of-the-art reversible logic gates and their real-world utility. While prior research has discussed these gates individually, this paper takes a novel approach by offering a holistic assessment of their performance, quantum cost, gate count, and practical applications, thereby presenting a comprehensive resource for researchers, engineers, and designers in the field. This innovative contribution plays a pivotal role in shaping the progress of energy-efficient and quantum computing systems as well as in optimizing VLSI chip designs for various applications, with a particular emphasis on enhancing cryptographic and data processing capabilities. The findings of this review aim to stimulate further research and development in reversible computing, contributing to the advancement of energy-efficient and information-preserving computing systems.

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Section: Applications Of Reversible Logic Gatesmentioning

confidence: 99%

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Tiwari,

Kadam,

Dudhedia

et al. 2024

MMEP

View full text Add to dashboard Cite

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“…A widespread technique for building fault-tolerant quantum circuits is to design them using only Clifford+T gates [30,32,33]. A circuit built exclusively with these gates will allow the use of error correction codes [34][35][36], which together with the aforementioned strategies will improve its error tolerance.…”

Section: Fault-tolerancementioning

confidence: 99%

Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders

et al. 2022

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Adders are one of the most interesting circuits in quantum computing due to their use in major algorithms that benefit from the special characteristics of this type of computation. Among these algorithms, Shor’s algorithm stands out, which allows decomposing numbers in a time exponentially lower than the time needed to do it with classical computation. In this work, we propose three fault-tolerant carry lookahead adders that improve the cost in terms of quantum gates and qubits with respect to the rest of quantum circuits available in the literature. Their optimal implementation in a real quantum computer is also presented. Finally, the work ends with a rigorous comparison where the advantages and disadvantages of the proposed circuits against the rest of the circuits of the state of the art are exposed. Moreover, the information obtained from such a comparison is summarized in tables that allow a quick consultation to interested researchers.

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“…The digital chips density is naturally raised as nano devices are produced in an effort to reduce power consumption and heat dissipation by this use. A number of methods were presented previously for improving the hardware capacity of the multipliers, but no one method provided sufficient results, because of lesser speed, power consumption, count of gates, garbage output, number of quantum costs are increased [18]. To overcome these issues, this work is proposed.…”

Section: Introductionmentioning

confidence: 99%

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

Raj

Kumar

Satyanarayana

2023

IRASE

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Most error-resilient media processing applications use multipliers as their basic building blocks. These are power-consumption and computationally intensive modules. In the existing works, several types of the multipliers were used to improve the hardware capacity, but those methods did not provide sufficient results. Therefore, in this manuscript, a Baugh-Wooley Multiplier design using Multiple Control Toffoli (MCT) and Multiple Control Fredrick gate (MCF) Reversible Logic gate (BWM-MCT-MCF) will be analyzed. Initially, Reversible Full Adder (RFA) is designed using Multiple Control Toffoli and Multiple Control Fredrick gate Reversible Logic gates. Then the proposed Reversible Full Adder is used in Baugh-Wooley Multiplier. By this, it reduces the hardware complexity with higher speed, lower area, lower power consumption. The proposed BWM-MCT-MCF multiplier is implemented in MATLAB, its performance shows lower Garbage output 22.78%, 24.88%, 20.95% compared with the existing designs, like BWM-FG-FRG, BWM-RL-TG, BWM-TG-FG respectively. Then the designed BWM-MCT-MCF is implemented using Xilinx ISE tool with the Virtex 5 device. From this, the performance of the proposed FPGA-BWM-MCT-MCF method shows lower delay 23.77%, 16.86% compared with the existing designs, like FPGA-BWM-RL-TG, FPGA-BWM-TG-FG respectively.

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Fault-tolerant quantum reversible full adder/subtractor: Design and implementation

Cited by 7 publications

References 25 publications

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Implementation of three efficient 4-digit fault-tolerant quantum carry lookahead adders

Baugh-Wooley Multiplier design using Multiple Control Toffoli and Multiple Control Fredkin reversible logic gates

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