Fault-tolerant resynthesis with dual-output LUTs

Abstract

We present a fault-tolerant post-mapping resynthesis for FPGAbased designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this architectural feature can be used to build redundancy for fault masking with limited area and performance overhead. Our algorithm improves reliability of a mapping by performing two basic operations: duplication (in which free configuration bits are used to duplicate a logic function whose value is obtained at the secondary output) and encoding (in which two copies of the same logic function are ANDed or ORed together in the fanout of the duplicated logic). The problem of fault tolerant post-mapping resynthesis is then formulated as the optimal duplication and encoding scheme that ensures the minimal circuit fault rate w.r.t. a stochastic single fault model. We present an ILP formulation of this problem and an efficient algorithm based on generalized network flow. On MCNC benchmarks, experimental results show that for combinational circuits the proposed approach improves meantime-to-failure(MTTF) by 27% with 4% area overhead, and the proposed approach with explicit area redundancy improves MTTF by 113% with 36% area overhead, compared to the baseline mapping by ABC. This provides a viable fault tolerance solution for non-mission critical applications compared to TMR (triple modular redundancy) which has a 5×-6× area overhead.

In-place decomposition for robustness in FPGA

“…For 10 largest combinational MCNC benchmark circuits synthesized by ABC mapper, FMD from [10] improves MTTF by 10% on average, but IPD improves MTTF by 1.43× for PLB similar to that in Xilinx Vertex-5 and by 2.70× for PLB similar to that in Altera Stratix-IV, when the conservative 20% utilization rate of carry chain is assumed.…”

“…For example, when the second output is used, an ALUT in an ALM can implement up to two 6-input functions with four inputs shared between the two ALUTs. To improve circuit reliability against SEU faults, Fully Masked Duplication (FMD) has been proposed in [10], where duplication of a function is performed by utilizing the unused second output of an LUT. Then, AN D or OR encodings for logic masking and therefore robustness enhancement are added at all fanout LUTs of a duplicated LUT when unused input pins are available for the fanout LUTs.…”

“…It does not change PLB level placement and routing, and therefore there is no PLB level penalty on timing, area and design closure. In contrast, the duplication (namely FMD) algorithm from [10] carries out duplication and encoding (called converging in this paper) in multiple PLBs. This needs extra interconnects between PLBs, resulting in a heavy penalty in area, delay and design closure.…”

“…dundancy as the original logic function is now implemented with extra circuitry (i.e., carry chain) and such redundancy is used explicitly to make the circuit more robust for SEUs. IPD offers clear advantages over duplication in [10]. Firstly, duplication implies two identical subfunctions.…”

“…1(b)). Leveraging decomposable LUTs and under-utilization of large-sized LUTs, [10] proposed to duplicate the logic inside a partially used LUT, and increase MTTF without increasing the number of LUTs. However, the encoding to combine the duplicated logic is done in the fanout LUTs.…”